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MOTOROLA

M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL

4- 1

SECTION 4

8-BIT BUS OPERATION

The following paragraphs describe control signal and bus operation for 8-bit operation

during data transfer operations, bus arbitration, bus error and halt conditions, and reset

operation. The 8-bit bus operations devices are the MC68008, MC68HC001 in 8-bit mode,

and MC68EC000 in 8-bit mode. The MC68HC001 and MC68EC000 select 8-bit mode by

grounding mode during reset.

4.1 DATA TRANSFER OPERATIONS

Transfer of data between devices involves the following signals:

1. Address bus A0 through highest numbered address line

2. Data bus D0 through D7

3. Control signals

The address and data buses are separate parallel buses used to transfer data using an

asynchronous bus structure. In all cases, the bus master must deskew all signals it issues

at both the start and end of a bus cycle. In addition, the bus master must deskew the

acknowledge and data signals from the slave device. For the MC68HC001 and

MC68EC000, UDS is held negated and D15–D8 are undefined in 8-bit mode.

The following paragraphs describe the read, write, read-modify-write, and CPU space

cycles. The indivisible read-modify-write cycle implements interlocked multiprocessor

communications. A CPU space cycle is a special processor cycle.

4.1.1 Read Cycle

During a read cycle, the processor receives one byte of data from the memory or from a

peripheral device. When the data is received, the processor internally positions the byte

appropriately.

The 8-bit operation must perform two or four read cycles to access a word or long word,

asserting the data strobe to read a single byte during each cycle. The address bus in 8-bit

operation includes A0, which selects the appropriate byte for each read cycle. Figure 4-1

and 4-2 illustrate the byte read-cycle operation.

Freescale Semiconductor, Inc.

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M68000 Datasheet(PDF) 39 Page - Freescale Semiconductor, Inc