AT89C55WD datasheet(30/34 Pages) SYC

30 / 34 page

1921D–MICRO–6/08

AT89C55WD

35. Shift Register Mode Timing Waveforms

36. AC Testing Input/Output Waveforms(1)

Note:

1. AC Inputs during testing are driven at V

CC - 0.5V for a logic 1 and 0.45V for a logic 0. Timing

measurements are made at V

IH min. for a logic 1 and VIL max. for a logic 0.

37. Float Waveforms

(1)

Note:

1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage

occurs. A port pin begins to float when a 100 mV change from the loaded VOH/VOL level

occurs.

34. Serial Port Timing: Shift Register Mode Test Conditions

The values in this table are valid for V

CC = 4.0V to 5.5V and Load Capacitance = 80 pF.

Symbol

Parameter

12 MHz Osc

Variable Oscillator

Units

Min

Max

Min

Max

XLXL

Serial Port Clock Cycle Time

1.0

12t

CLCL

µs

tQVXH

Output Data Setup to Clock Rising Edge

700

10tCLCL-133

tXHQX

Output Data Hold After Clock Rising Edge

2tCLCL-80

XHDX

Input Data Hold After Clock Rising Edge

tXHDV

Clock Rising Edge to Input Data Valid

700

10tCLCL-133

XHDV

QVXH

XLXL

XHDX

XHQX

ALE

INPUT DATA

CLEAR RI

OUTPUT DATA

WRITE TO SBUF

INSTRUCTION

CLOCK

SET TI

SET RI

VALID

0.45V

TEST POINTS

- 0.5V

0.2 V

+ 0.9V

0.2 V

- 0.1V

LOAD

+ 0.1V

Timing Reference

Points

LOAD

- 0.1V

LOAD

+ 0.1V

- 0.1V

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