SN54HC166, SN74HC166

8BIT PARALLELLOAD SHIFT REGISTERS

SCLS117D − DECEMBER 1982 − REVISED SEPTEMBER 2003

5

POST OFFICE BOX 655303

timing requirements over recommended operating free-air temperature range (unless otherwise

noted)

VCC

TA = 25°C

SN54HC166

SN74HC166

UNIT

VCC

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

2 V

6

4.2

5

fclock

Clock frequency

4.5 V

31

21

25

MHz

fclock

Clock frequency

6 V

36

25

29

MHz

2 V

100

150

125

CLR low

4.5 V

20

30

25

tw

Pulse duration

CLR low

6 V

17

26

21

ns

tw

Pulse duration

2 V

80

120

100

ns

CLK high or low

4.5 V

16

24

20

CLK high or low

6 V

14

20

17

2 V

145

220

180

SH/LD high before CLK

↑

4.5 V

29

44

36

SH/LD high before CLK

↑

6 V

25

38

31

2 V

80

120

100

SER before CLK

↑

4.5 V

16

24

20

SER before CLK

↑

6 V

14

20

17

2 V

100

150

125

tsu

Setup time

CLK INH low before CLK

↑

4.5 V

20

30

25

ns

tsu

Setup time

CLK INH low before CLK

↑

6 V

17

26

21

ns

2 V

80

120

100

Data before CLK

↑

4.5 V

16

24

20

Data before CLK

↑

6 V

14

20

17

2 V

40

60

50

CLR inactive before CLK

↑

4.5 V

8

12

10

CLR inactive before CLK

↑

6 V

7

10

9

2 V

0

0

0

SH/LD high after CLK

↑

4.5 V

0

0

0

SH/LD high after CLK

↑

6 V

0

0

0

2 V

5

5

5

SER after CLK

↑

4.5 V

5

5

5

th

Hold time

SER after CLK

6 V

5

5

5

ns

th

Hold time

2 V

0

0

0

ns

CLK INH high after CLK

↑

4.5 V

0

0

0

CLK INH high after CLK

↑

6 V

0

0

0

2 V

5

5

5

Data after CLK

↑

4.5 V

5

5

5

Data after CLK

6 V

5

5

5