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AD9984A Datasheet(PDF) 16 Page - Analog Devices |
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AD9984A Datasheet(HTML) 16 Page - Analog Devices |
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16 / 44 page  AD9984A Rev. 0 | Page 16 of 44 SYNC PROCESSING The inputs of the sync processing section of the AD9984A are combinations of digital Hsyncs and Vsyncs, analog sync-on- green or sync-on-Y signals, and an optional external coast signal. From these signals, the part generates a precise, jitter- free clock from its PLL, an odd/even-field signal, HSOUT and VSOUT signals, a count of Hsyncs per Vsync, and a programmable SOGOUT. The main sync processing blocks are the sync slicer, sync separator, Hsync filter, Hsync regenerator, Vsync filter, and coast generator. • The sync slicer extracts the sync signal from the green graphics or luminance video signal that is connected to the SOGINx inputs, and outputs a digital composite sync. • The sync separator extracts Vsync from the composite sync signal, which can come from either the sync slicer or the HSYNCx inputs. • The Hsync filter is used to eliminate any extraneous pulses from the HSYNCx or SOGINx inputs, outputting a clean, low-jitter signal that is appropriate for mode detection and clock generation. • The Hsync regenerator is used to recreate a clean, although not low jitter, Hsync signal that can be used for mode detection and counting Hsyncs per Vsync. • The Vsync filter is used to eliminate spurious Vsyncs, main- tain a stable timing relationship between the Vsync and Hsync output signals, and generate the odd/even field output. • The coast generator creates a robust coast signal to allow the PLL to maintain its frequency in the absence of Hsync pulses. AD9984A SOGOUT HSYNC VSYNC COAST COAST SELECT 0x18:7 DATACK SOGIN0 EXTCK/COAST VSYNC1 MUX MUX MUX MUX MUX MUX MUX MUX VSYNC0 HSYNC1 HSYNC0 HSOUT VSOUT/A0 SOGIN1 HSYNC SELECT 0x12:6 FILTERED HSYNC ACTIVITY DETECT ACTIVITY DETECT ACTIVITY DETECT ACTIVITY DETECT ACTIVITY DETECT ACTIVITY DETECT POLARITY DETECT POLARITY DETECT POLARITY DETECT POLARITY DETECT SYNC SLICER SYNC SLICER PLL CLOCK GENERATOR O/E FIELD CHANNEL SELECT 0x1E:6 HSYNC FILTER AND REGENERATOR REGENERATED HSYNC SET POLARITY SET POLARITY HSYNC/VSYNC COUNTER REG 0x26, 0x27 SET POLARITY SET POLARITY VSYNC FILTERED VSYNC VSYNC FILTER EN 0x14:2 VSYNC FILTER EN 0x14:2 PLL SYNC FILTER EN 0x20:2 SP SYNC FILTER EN 0x20:1 SOGOUT SELECT 0x1D:1,0 MUX Figure 9. Sync Processing Block Diagram |
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