CAT25640 datasheet(9/16 Pages) CATALYST

9 / 16 page

CAT25640

Doc. No. MD-1128 Rev. B

Characteristics subject to change without notice

SCK

BYTE ADDRESS*

* Please check the Byte Address Table (Table 5).

DATA OUT

MSB

HIGH IMPEDANCE

OPCODE

READ OPERATIONS

Read from Memory Array

To read from memory, the host sends a READ

instruction followed by a 16-bit address (see Table 5 for

the number of significant address bits).

After receiving the last address bit, the CAT25640 will

respond by shifting out data on the SO pin (as shown

in Figure 8). Sequentially stored data can be read out

by simply continuing to run the clock. The internal

address pointer is automatically incremented to the

next higher address as data is shifted out. After

reaching the highest memory address, the address

counter “rolls over” to the lowest memory address,

and the read cycle can be continued indefinitely. The

read operation is terminated by taking CS

¯¯ high.

Read Status Register

To read the status register, the host simply sends a

RDSR command. After receiving the last bit of the

command, the CAT25640 will shift out the contents of

the status register on the SO pin (Figure 9). The

status register may be read at any time, including

during an internal write cycle.

Figure 8. READ Timing

Note:

Dashed Line = mode (1, 1) - - - - - -

Figure 9. RDSR Timing

Note:

Dashed Line = mode (1, 1) - - - - - -

911

SCK

DATA OUT

MSB

HIGH IMPEDANCE

OPCODE

CAT25640 Datasheet(PDF) 9 Page - Catalyst Semiconductor

CAT25640 Datasheet(HTML) 9 Page - Catalyst Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Datasheet Download

Link URL