HT46R52A datasheet(13/42 Pages) HOLTEK

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HT46R51A/HT46R52A

Rev. 1.10

September 20, 2007

Reset(Power On)

WDT Time-out

(Normal Operation)

RES Reset

(Normal Operation)

RES Reset

(HALT)

WDT Time-out

(HALT)*

1111 1111

uuuu uuuu

PAC

1111 1111

uuuu uuuu

---1 1111

---u uuuu

PBC

---1 1111

---u uuuu

---- ---1

---- ---u

PDC

---- ---1

---- ---u

PWM

xxxx xxxx

uuuu uuuu

ADRL

xxxx ----

uuuu ----

ADRH

xxxx xxxx

uuuu uuuu

ADCR

0100 0000

uuuu uuuu

ACSR

---- --00

---- --uu

Note:

²*² stands for ²warm reset²

²u² stands for ²unchanged²

²x² stands for ²unknown²

Timer/Event Counter

Only one timer/event counter (TMR) are implemented in

the microcontroller. The timer/event counter contains an

8-bit programmable count-up counter and the clock may

come from an external source or an internal clock

source. An internal clock source comes from fSYS. The

external clock input allows the user to count external

events, measure time intervals or pulse widths, or to

generate an accurate time base.

There are two registers related to the Timer/event coun-

ter; TMR (0DH), TMRC (0EH). Writing TMR will transfer

the specified data to timer/event counter registers.

Reading the TMR will read the contents of the

timer/event counter. The TMRC is a control register,

which defines the operating mode, counting enable or

disable and an active edge.

The TM0 and TM1 bits define the operation mode. The

event count mode is used to count external events,

which means that the clock source is from an external

(TMR) pin. The timer mode functions as a normal timer

with the clock source coming from the internal selected

clock source. Finally, the pulse width measurement

mode can be used to count the high or low level duration

of the external signal (TMR), and the counting is based

on the internal selected clock source.

In the event count or timer mode, the timer/event coun-

ter starts counting at the current contents in the

timer/event counter and ends at

. Once an overflow

occurs, the counter is reloaded from the timer/event

counter preload register, and generates an interrupt re-

quest flag (TF; bit 5 of the INTC ). In the pulse width

measurement mode with the values of the TON and TE

bits equal to 1, after the TMR has received a transient

from low to high (or high to low if the TE bit is

²0²), it will

start counting until the TMR returns to the original level

and resets the TON. The measured result remains in the

timer/event counter even if the activated transient oc-

curs again. In other words, only 1-cycle measurement

can be made until the TON is set. The cycle measure-

ment will re-operate as long as it receives further tran-

sient pulse. In this operation mode, the timer/event

counter begins counting not according to the logic level

but to the transient edges. In the case of counter over-

flows, the counter is reloaded from the timer/event coun-

ter register and issues an interrupt request, as in the

other two modes, i.e., event and timer modes.

To enable the counting operation, the Timer ON bit

(TON; bit 4 of the TMRC) should be set to

²1².Inthe

pulse width measurement mode, the TON is automati-

cally cleared after the measurement cycle is completed.

But in the other two modes, the TON can only be reset

by instructions. The overflow of the timer/event counter

is one of the wake-up sources and can also be applied

to a PFD (Programmable Frequency Divider) output at

PA3 by options. No matter what the operation mode is,

writing a

²0² to ETI (bit2 of the INTC) disables the re-

lated interrupt service. When the PFD function is se-

lected, executing

²SET [PA].3² instruction to enable the

PFD output and executing

²CLR [PA].3² instruction to

disable the PFD output.

In the case of timer/event counter OFF condition, writing

data to the timer/event counter preload register also re-

loads that data to the timer/event counter. But if the

timer/event counter is turn on, data written to the

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