HV633 datasheet(4/11 Pages) SUTEX

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HV633

Option 1

Option 2

BIAS

CTL

BIAS

CTL

(V)

( ý )

(mA)

(V)

( ý )

(mA)

0.1

56K

-1.0

56K

1.0

56K

-2.0

56K

5.5

Table 1:

Schemes to control I

PP bias current, typical IPP

HV633

VCTL

RCTL

VBIAS

Pin #

Name

Function

30-36

D1-D7

Inputs for binary-format parallel data.

SC (Shift Clock)

Triggers data on both rising and falling edges. This implies that the data rate is always twice the clock

rate (data rate = 20MHz max if clock rate = 10MHz max).

CSI (Chip

Input pin for the chip select pulse (when DIR is high).

Select Input)

Output pin for the chip select pulse (when DIR is low).

CSO (Chip

Input pin for the chip select pulse (when DIR is low).

Select Output)

Output pin for the chip select pulse (when DIR is high).

Input for a pulse whose rising edge causes data from the input latches to enter the comparator latches,

(Load Count)

and whose falling edge initiates the conversion of this binary data to an output level (D-to-A).

Also, the HV

OUT will clear to zero after the load count is initiated.

CC (Count Clock) Input to the count clock generator whose increments are compared to the data in the comparator latches.

18, 47

High-voltage ramp input for charging the output stage hold capacitors (CH).

This input can be linear or non-linear as desired.

DIR

When this pin is connected to VDD, input data is shifted in ascending order,

i.e., corresponding to HV

OUT1 to HVOUT32. When connected to LVGND, input data is shifted

in descending order, i.e., corresponding to HV

OUT32 to HVOUT1.

27, 38

LVGND

This is ground for the logic section.

HVGND and LVGND should be connected together externally.

17, 48

HVGND

This is ground for the high-voltage (output) section.

HVGND and LVGND should be connected together externally.

19, 45

This input biases the output source followers.

1-16

HVOUT1-

High-voltage outputs.

49-64

OUT32

VDD (Analog)

Low-voltage analog supply voltage.

DD (Digital)

Low-voltage digital supply voltage.

CTL

Voltage supply pin to prevent output voltage from being affected by its adjacent outputs (V

CTL = 2V for a

particular panel). The combination of V

CTL and RCTL will reduce the output voltage variation to less than

±0.2V of delta voltage between high voltage outputs of the same level at all gray levels.

CTL

Current sense resistor to ground to prevent output voltage from being affected by its adjacent outputs

(RCTL = 56Ký for a particular panel). See VCTL function above.

Pin Definitions

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