2

HV732DB1

The PCB Layout Techniques

The big thermal pad at the bottom of the HV732 package is

connected to the V

it always has the highest potential of the chip. V

connection of the IC’s substrate. The other two smaller pieces

of the slab at the bottom of the chip are the drains of the high

voltage output P-channel and N-channel MOSFETs. They

are connected to high voltage outputs. PCB designers need

to pay attention to the connecting the traces as high-voltage

and high-speed traces. In particular, low capacitance to the

ground plane and more trace spacing needs to be applied in

this situation.

High-speed PCB trace design practices that are compatible

with about 50MHz to 100MHz operating speed are used

for the demo board PCB layout. The internal circuitry of the

HV732 can operate at a quite high frequency, with the primary

speed limitation being load capacitance. Because of this high

speed and the high transient currents that result when driving

capacitive loads, the supply voltage bypass capacitors and

the driver to the FET’s gate-coupling capacitors should be as

close to the pins as possible. The GND and AGND pin pads

should have low inductance feed-through connections that

are connected directly to a solid ground plane. The V

V

so they should be provided with a low-impedance bypass

capacitor at the chip’s pins. A ceramic capacitor of 0.47µF to

1.0µF may be used. Minimize the trace length to the ground

plane, and insert a ferrite bead in the power supply lead

to the capacitor to prevent resonance in the power supply

lines. For applications that are sensitive to jitter and noise

and are using multiple HV732 ICs, insert another ferrite bead

between V

Pay particular attention to minimizing trace lengths and

using sufficient trace width to reduce inductance. Surface

mount components are highly recommended. Since the

output impedance of HV732’s high voltage power stages are

very low, in some cases it may be desirable to add a small

value resistor in series with the output TX

better waveform integrity at the load terminals. This will, of

course, reduce the output voltage slew rate at the terminals

of a capacitive load. The same technique can be applied to

the driver output to P

Be aware of the parasitic coupling from the outputs to the

input signal terminals of HV732. This feedback may cause

oscillations or spurious waveform shapes on the edges of

signal transitions. Since the input operates with signals

down to 1.8V, even small coupling voltages may cause

problems. Use of a solid ground plane and good power and

signal layout practices will prevent this problem. Also ensure

that the circulating ground return current from a capacitive

load cannot react with common inductance to create noise

voltages in the input logic circuitry.

Testing the Integrated Pulser

This HV732 pulser demo board should be powered up with

multiple lab DC power supplies with current limiting functions.

The following power supply voltages and current limits have

been used in the testing: V

V

= +9V to +12V 10mA, V

LN

= -5V 5.0mA. V

need to be connected to the same voltage. If the V

needs to be included in the V

circuits, then a higher current limit should be set.

The power-up or down sequences of the voltage supply

ensure that the HV732 chip substrate, V

always at the highest potential of all the voltages supplied

to the IC.

The on-board dummy load 220pF/1kΩ should be connected

to the high voltage pulser output through the solder jumper

when using an oscilloscope high impedance probe to meet

the typical loading conditions. For looking into the different

loading conditions, one may change the values of RC within

the current and power limit of the device.

In order to drive piezo transducers with a cable, one should

match the output load impendence properly to avoid cable

and large transducer reflections. A 70Ω to 75Ω coaxial cable

is recommended. The coaxial cable end should be soldered

to the HV

leads.

All the on-board test points are designed to work with the

high impedance probe of the oscilloscope. Some probes

may have limited input voltage. When using the probe on

these high voltage test-points, make sure that V

not exceed the probe limit. Using the high impendence

oscilloscope probe for the on-board test points, it is important

that the ground leads to the circuit board ground plane are

as short as possible.

There are examples of the HV732 output waveforms and

pulser input shown in the diagrams on pages 5-8.

Precautions need be applied to not overlap the logic-high

time periods of the control signals. Permanent damage

to the device may occur when cross-conduction or shoot-

through currents exceed the device maximum limits. The

input logic pins should connect to the low impedance CMOS

logic control circuit outputs or 1kΩ pull-up or pull-down

resistors during the test. Leave these pins floating or logic

state unknown may damage the device.