5

 2006 Semtech Corp.

www.semtech.com

SC486

POWER MANAGEMENT

Notes:

(1) The output voltage will have a DC regulation level higher than the error-comparator threshold by 50% of the

ripple voltage.

(2) Using a current sense resistor, this measurement relates to PGND1 minus the voltage of the source on the

low-side MOSFET.

(3) clks = switching cycles, consisting of one high side and one low side gate pulse.

(4) Guaranteed by design.

(5) Thermal shutdown latches both outputs (VTT and VDDQ) off, requiring VCCA or EN/PSV cycling to reset.

(6) VTT soft start ramp rate is 6mV/µs typical unless VDDQ/2 ramp rate is slower. If this is true, VTT soft start

ramps at 6mV/µs (typ.) until it reaches VDDQ/2, and then tracks it.

(7) See Shoot-Through Delay Timing Diagram below.

(8) Semtech’s SmartDriver™ FET drive first pulls DH high with a pull-up resistance of 10

Ω (typ.) until LX = 1.5V

(typ.). At this point, an additional pull-up device is activated, reducing the resistance to 2

Ω (typ.). This negates the

need for an external gate or boost resistor.

(9) Provided operation below T

(10) This device is ESD sensitive. Use of standard ESD handling precautions is required.

tplhDL

tplhDH

LX

DL

DL

DH

r

e

t

e

m

a

r

a

Ps

n

o

i

t

i

d

n

o

CC

°

5

2C

°

5

2

1

o

t

C

°

0

4

-s

t

i

n

U

n

i

Mp

y

Tx

a

Mn

i

Mx

a

M

)

.

t

n

o

C

(

s

e

v

i

r

D

e

t

a

G

e

c

n

a

t

s

i

s

e

R

p

U

-l

l

u

P

L

Dh

g

i

h

L

D2

4

Ω

t

n

e

r

r

u

C

e

c

r

u

o

S

L

DV

L

D

V

5

.

2

=3

.

1A

e

c

n

a

t

s

i

s

e

R

n

w

o

D

-l

l

u

P

H

DV

5

=

X

L

-

T

S

B

,

w

o

l

H

D2

4

Ω

e

c

n

a

t

s

i

s

e

R

p

U

-l

l

u

P

H

D

)

8

(

V

5

=

X

L

-

T

S

B

,

h

g

i

h

H

D2

4

Ω

t

n

e

r

r

u

C

e

c

r

u

o

S

/

k

n

i

S

H

DV

H

D

V

5

.

2

=3

.

1A

e

c

n

a

t

s

i

s

e

R

p

U

-l

l

u

P

T

T

VF

E

R

<

S

T

T

V5

2

.

05

4

.

0

Ω

e

c

n

a

t

s

i

s

e

R

n

w

o

D

-l

l

u

P

T

T

VF

E

R

>

S

T

T

V5

2

.

05

4

.

0

Ω

t

n

e

r

r

u

C

e

c

r

u

o

S

/

k

n

i

S

k

a

e

P

T

T

V

)

9

(

6

.

30

.

2A

Test Conditions: V

Electrical Characteristics (Cont.)

Shoot-Through Delay Timing Diagram