7-237

9

7

VP0535

VP0540

Advanced DMOS Technology

These enhancement-mode (normally-off) transistors utilize a

vertical DMOS structure and Supertex’s well-proven silicon-gate

manufacturing process. This combination produces devices with

the power handling capabilities of bipolar transistors and with the

high input impedance and positive temperature coefficient inher-

ent in MOS devices. Characteristic of all MOS structures, these

devices are free from thermal runaway and thermally-induced

secondary breakdown.

Supertex’s vertical DMOS FETs are ideally suited to a wide range

of switching and amplifying applications where high breakdown

voltage, high input impedance, low input capacitance, and fast

switching speeds are desired.

Note: See Package Outline section for dimensions.

P-Channel Enhancement-Mode

Vertical DMOS FETs

Package Options

High Reliability Devices

See pages 5-4 and 5-5 for MILITARY STANDARD Process

Flows and Ordering Information.

Absolute Maximum Ratings

Drain-to-Source Voltage

Drain-to-Gate Voltage

Gate-to-Source Voltage

± 20V

Operating and Storage Temperature

-55°C to +150°C

Soldering Temperature*

300°C

Applications

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displays, bipolar transistors, etc.)

Features

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Order Number / Package

(max)

(min)

TO-39

TO-92

-350V

75Ω

-200mA

VP0535N2

VP0535N3

VP0535ND

-400V

75Ω

-200mA

—

VP0540N3

VP0540ND

TO-39

TO-92

Ordering Information

S G D

D G S

Case: DRAIN

– OBSOLETE

–