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SC2677B Datasheet(PDF) 5 Page - Semtech Corporation |
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SC2677B Datasheet(HTML) 5 Page - Semtech Corporation |
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5 / 19 page ![]() 5 © 2004 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2677B EXP EXP EXP EXP EXPANDED PIN DESCRIPTION ANDED PIN DESCRIPTION ANDED PIN DESCRIPTION ANDED PIN DESCRIPTION ANDED PIN DESCRIPTION Pin 1 Pin 1 Pin 1 Pin 1 Pin 1, 2 , 2 , 2 , 2 , 24: 4: 4: 4: 4: (CS2+, CS1+) Current sense amplifier (for OCP protection) non-inverting inputs. Pin 2, 23: Pin 2, 23: Pin 2, 23: Pin 2, 23: Pin 2, 23: (CS2-, CS1-) Current-Sense Amplifier (for OCP protection) inverting inputs. Pin 3: Pin 3: Pin 3: Pin 3: Pin 3: (VREF) Internal 0.5V reference. Connected to the “+” input of the Master Channel Error Amplifier. Pin 4: Pin 4: Pin 4: Pin 4: Pin 4: (FREQ) External frequency adjustment. Connect a resistor to AGND to set the switching frequency. Please see more information in “Application” section. Pin 5: Pin 5: Pin 5: Pin 5: Pin 5: (VCC) Bias pin for the controller. Connect a ceramic decoupling capacitor from this pin to AGND with minimum trace length. Pin 6: Pin 6: Pin 6: Pin 6: Pin 6: (+IN2) “+” input of the slave error amplifier. Pin 7, 18: Pin 7, 18: Pin 7, 18: Pin 7, 18: Pin 7, 18: (-IN2, -IN1) “-” inputs of the Error Amplifiers. Pin 8, 1 Pin 8, 1 Pin 8, 1 Pin 8, 1 Pin 8, 17 77 7 7::::: (COMP2, COMP1) Compensation pins of the Error Amplifiers. Pin 9, 1 Pin 9, 1 Pin 9, 1 Pin 9, 1 Pin 9, 16: 6: 6: 6: 6: (BST2, BST1) Supply pins for the high side drivers. Usually connected to bootstrap circuit. Pin 10, 15: Pin 10, 15: Pin 10, 15: Pin 10, 15: Pin 10, 15: (DH2, DH1) Gate drive pins for the top MOSFETs. Requires a small series resistor. Pin 11, 14: Pin 11, 14: Pin 11, 14: Pin 11, 14: Pin 11, 14: (DL2, DL1) Gate drive pins for the bottom MOSFETs. Requires a small series resistor. Pin 12: Pin 12: Pin 12: Pin 12: Pin 12: (PGND) Power GND. Return of the high side and low side gate drivers. Pin 13: Pin 13: Pin 13: Pin 13: Pin 13: (BSTC) Supply pin for bottom MOSFET gate drivers. Pin 19: Pin 19: Pin 19: Pin 19: Pin 19: (PHASING) This pin controls the phase shift between Master and Slave for optimum noise immunity. Use a resistive di- vider from the FREQ pin (pin 2) to AGND, and connect the tap of the resistive divider to pin 17. Please see more information in “Application” section. Pin 20: Pin 20: Pin 20: Pin 20: Pin 20: (SS/ENA) Soft Start pin. Connect a ceramic capacitor from this pin to AGND, and there is an internal current source charg- ing up this capacitor during Soft Start. The PWM opera- tion can be disabled if this pin is pulled low. Pin 2 Pin 2 Pin 2 Pin 2 Pin 21: 1: 1: 1: 1: (PWRGD) Power Good signal. This is an open collector output. It is pulled low internally if output voltage is outside the Power Good window. Pin 22: Pin 22: Pin 22: Pin 22: Pin 22: (GND) Analog GND. Return of the analog signals and bias of the chip. e c i v e De c i v e D e c i v e D e c i v e De c i v e D ) 1 () 1 ( ) 1 ( ) 1 () 1 ( e g a k c a Pe g a k c a P e g a k c a P e g a k c a Pe g a k c a P T R T S T I B 7 7 6 2 C S ) 2 () 2 ( ) 2 ( ) 2 () 2 ( 4 2 - P O S S T T R T E T B 7 7 6 2 C S ) 2 () 2 ( ) 2 ( ) 2 () 2 ( P D E 4 2 - P O S S T 1 - B V E B 7 7 6 2 C Sd r a o B n o i t a u l a v E e r a h S t n e r r u C 2 - B V E B 7 7 6 2 C Sd r a o B n o i t a u l a v E l e n n a h C l a u D Notes: Notes: Notes: Notes: Notes: (1) Only available in tape and reel packaging. A reel con- tains 2500 devices. (2) Lead free package. Device is fully WEEE and RoHS compliant. Top View (TSSOP-24 Pin) Pin Configuration Ordering Information Pin Descriptions |
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