SC4603IMSTRT datasheet(12/16 Pages) SEMTECH

12 / 16 page

 2004 Semtech Corp.

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SC4603

POWER MANAGEMENT

Applications Information - (Cont.)

After the compensation, the converter will have the

following loop gain:

)

(

)

(

)

(

COMP

PWM

⋅

Where:

PWM = PWM gain and

M = 1.0V, ramp peak to valley voltage of SC4603.

The design guidelines for the SC4603 applications are

as following:

1. Set the loop gain crossover corner frequency

C for given switching corner frequency

S =2 πfs,

2. Place an integrator at the origin to increase DC

and low frequency gains.

3. Select

Z1 and ωZ2 such that they are placed

near

O to damp the peaking and the loop gain

has a -20dB/dec rate to go across the 0dB

line for obtaining a wide bandwidth.

4. Cancel the zero from C

4’s ESR by a compensa-

tor pole

P1 (ωP1 = ωESR = 1/( RCC4)),

5. Place a high frequency compensator pole

ωp

(

ωp

2 = πpfs) to get the maximum attenuation of

the switching ripple and high frequency noise

with the adequate phase lag at

The compensated loop gain will be as given in Figure 4:

-20dB/dec

0dB

ωZ1

ωZ2

ESR

ωo

Loop gain T(s)

Power stage GVD(s)

-40dB/dec

Figure 4. Asymptotic diagrams of power stage and its

loop gain.

Layout Guidelines

In order to achieve optimal electrical, thermal and noise

performance for high frequency converters, special at-

tention must be paid to the PCB layouts. The goal of lay-

out optimization is to identify the high di/dt loops and

minimize them. The following guideline should be used to

ensure proper functions of the converters.

1. A ground plane is recommended to minimize noises

and copper losses, and maximize heat dissipation.

2. Start the PCB layout by placing the power compo-

nents first. Arrange the power circuit to achieve a

clean power flow route. Put all the connections on

one side of the PCB with wide copper filled areas if

possible.

3. The V

CC bypass capacitor should be placed next to

the VCC and GND pins.

4. The trace connecting the feedback resistors to the

output should be short, direct and far away from the

noise sources such as switching node and switching

components.

5. Minimize the traces between PDRV/NDRV and the

gates of the MOSFETs to reduce their impedance to

drive the MOSFETs.

6. Minimize the loop including input capacitors, top/bot-

tom MOSFETs. This loop passes high di/dt current.

Make sure the trace width is wide enough to reduce

copper losses in this loop.

7. ISET and PHASE connections to P-MOSFET for cur-

rent sensing must use Kelvin connections.

Where

)

(

⋅

)

(

⋅

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