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HT82V24 Datasheet(PDF) 4 Page - Holtek Semiconductor Inc

Part # HT82V24
Description  16-Bit, 15MSPS, 3-Channel CCD/CIS Analog Signal Processor
PDF  21 Pages
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Manufacturer  HOLTEK [Holtek Semiconductor Inc]
Direct Link  http://www.holtek.com
Logo HOLTEK - Holtek Semiconductor Inc

HT82V24 Datasheet(HTML) 4 Page - Holtek Semiconductor Inc

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background image
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
VDD
Conditions
Temperature Range
tA
Operating
¾¾
0
¾
70
°C
Power Consumption
Ptot3
Total Power Consumption (3CH)
¾¾
¾
380
¾
mW
Ptot2
Total Power Consumption (2CH)
¾¾
¾
340
¾
mW
Ptot1
Total Power Consumption (1CH)
¾¾
¾
300
¾
mW
Note:
²*² means the full-scale input range select by configuration register
Timing Specification
Symbol
Parameter
Min.
Typ.
Max.
Unit
Clock Parameters
tPRA
3-channel pixel rate
200
¾¾
ns
tPRB
2-channel (Even-Odd) pixel rate
133
¾¾
ns
tPRC
1-channel pixel rate
66
¾¾
ns
tADCLK
ADCCLK Pulse Width
33
¾¾
ns
tC1
CDSCLK1 Pulse Width
15
30
¾
ns
tC2
CDSCLK2 Pulse Width
15
30
¾
ns
tC1C2
CDSCLK1 Falling to CDSCLK2 Rising
0
¾¾
ns
tADC2
ADCCLK Rising to CDSCLK2 Falling
0
¾¾
ns
tC2ADR
CDSCLK2 Rising to ADCCLK Rising
5
¾¾
ns
tC2ADF
CDSCLK2 Falling to ADCCLK Falling
30
¾¾
ns
tC2C1
CDSCLK2 Falling to CDSCLK1 Rising
30
¾¾
ns
tAD
Analog Sampling Delay
¾
5
¾
ns
Serial Interface
fSCLK
Maximum SCLK Frequency
10
¾¾
MHz
tLS
SLOAD to SCLK Setup Time
10
¾¾
ns
tLH
SCLK to SLOAD Hold Time
10
¾¾
ns
tDS
SDATA to SCLK Rising Setup Time
10
¾¾
ns
tDH
SCLK Rising to SDATA Hold Time
10
¾¾
ns
tRDV
Falling to SDATA Valid
10
¾¾
ns
Data Output
tOD
Output Delay
¾
12
¾
ns
HT82V24
Rev. 1.00
4
September 7, 2005



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