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SC339

PRELIMINARY

POWER MANAGEMENT

Applications Information

Theory Of Operation

The SC339 linear FET controller provides a simple

way to drive an N-channel MOSFET to produce tightly

regulated output voltages from an available,

higher, supply voltage. It takes its power from

the 5V system supply, drawing 130μA (typ) while

operating.

It contains an internal bandgap reference which is

compared to the output voltage via a resistor divider.

The resistor divider is external and user selectable. The

drive pin (DRV) can pull up to a guaranteed minimum of

4.7V. Thus, the device can be used to regulate a large

range of output voltages by careful selection of the

external MOSFETs (see Component Selection on this

page).

The SC339 includes an active high enable control (EN). If

this pin is pulled low, the drive pin is pulled low, turning

off the N-channel MOSFET. If the pin is pulled up to 2.8V

≤ V

be allowed to float.

The SC339 has a power good output (PGD) which is an

open drain output that pulls low if the related output is

below the power good threshold (-12% of the programmed

output voltage typical). The power good circuitry is active

if the device is enabled, regardless of the state of the

over-current latch.

Anover-currentprotectioncircuitmonitorstheoutputvoltage.

If the output voltage drops below 50% (typical) of nominal,

as would occur during an over-current or short condition, the

device will pull the drive pin low and latch off. Toggle the

power supply or enable pin to reset the latch condition.

Drive Output

The drive output is source and sink capable. The drivers

both source and sink 20mA of current typically at 5V IN.

Soft-Start and Power Good Timing

At start-up, the internal reference is switched from its

normal 0.5VDC to a 1ms (typical) linear ramp. The output

voltage tracks the ramp until 0.5V is reached. The PWRGD

signal is held low until the output has been in regulation

approximately 500μsec to allow the output voltage to

stabilize. The power-up is very smooth and monotonic.

OCP and Power Supply Sequencing

The SC339 has output under-voltage protection that

looks at the output to see if it is: a) less than 50% (typi-

cal) of its nominal value and, b) V

within 350mV (typical) of maximum. If both of these

criteria are met, there is a 1ms (typical) delay and

then the output is shut down. This provides inherent

immunity to UV shutdown at start-up (which may occur while

the output capacitors are being charged).

At start-up, it is necessary to ensure the power

supplies and enable are sequenced correctly to

avoid erroneous latch-off. For UV latch-off not to oc-

cur at start-up due to sequencing issues, the volt-

age supplied to the MOSFET drain should be greater

than the output under-voltage threshold when that

output is enabled. This assumes that the drop through the

pass MOSFET is negligible. If not, then this drop needs to

be taken into account also since:

V

If the supply to the SC339 IN pin comes up before the

supply to the MOSFET drain, then that output should be

enabled after the supply to the MOSFET drain is applied

- the power good signal for this rail would be ideal. If the

power supply to the MOSFET drain comes up before the

power supply to the SC339 IN pin, then the output can either

be enabled with the supply to the IN pin or afterwards.

Please note the following example:

SC339 powered from 5V, the MOSFET (V

1.8V, set for 1.5V

60% (over temperature) of 1.5V, or 0.9V. The typical enable

threshold is ~2.4V, see Figure 1 on Page 7.

Component Selection

Output Capacitors: low ESR capacitors such as Sanyo

POSCAPs or Panasonic SP-caps are recommended for

bulk capacitance, with ceramic bypass capacitors for

decoupling high frequency transients. Ceramic output

capacitors may be used; however, use of ceramic output

capacitors requires compensation on the DRV output.