DS1986

21 of 27

Read/Write Time Slots

The definitions of write and read time slots are illustrated in Figure 10. All time slots are initiated by the

master driving the data line low. The falling edge of the data line synchronizes the DS1986 to the master

by triggering a delay circuit in the DS1986. During write time slots, the delay circuit determines when the

DS1986 will sample the data line. For a read data time slot, if a “0” is to be transmitted, the delay circuit

determines how long the DS1986 will hold the data line low overriding the 1 generated by the master. If

the data bit is a “1”, the iButton will leave the read data time slot unchanged.

PROGRAM PULSE

To copy data from the 8-bit scratchpad to the EPROM Data or Status Memory, a program pulse of 12

volts is applied to the data line after the bus master has confirmed that the CRC for the current byte is

correct. During programming, the bus master controls the transition from a state where the data line is

idling high via the pull-up resistor to a state where the data line is actively driven to a programming

voltage of 12 volts providing a minimum of 10 mA of current to the DS1986. This programming voltage

(Figure 11) should be applied for 480

µs, after which the bus master returns the data line to an idle high

state controlled by the pull-up resistor. Note that due to the high voltage programming requirements for

any 1-Wire EPROM device, it is not possible to multi-drop non-EPROM based 1-Wire devices with the

DS1986 during programming. An internal diode within the non-EPROM based 1-Wire devices will

attempt to clamp the data line at approximately 8 volts and could potentially damage these devices.

INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES” Figure 9

Regular Speed

Overdrive Speed

480

48

480

15

2

60

be less than 960

µs.

RESISTOR

MASTER

DS1986