TMS320F28044 datasheet(21/107 Pages) TI

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3.1

Memory Map

0x00 0000

Block Start

Address

Data Space

M0 SARAM (1K y 16)

0x00 0400

0x00 0800

0x00 0D00

0x00 6000

0x00 7000

0x00 8000

0x00 9000

0x00 A000

0x3D 7800

0x3D 7C00

0x3F 7FF8

0x3F 8000

0x3F 9000

0x3F A000

0x3F F000

0x3F FFC0

OTP

(1 K y 16, Secure Zone)

FLASH

64 K y 16, Secure Zone)

Boot ROM (4 K y 16)

Reserved

M1 SARAM (1K y 16)

L0 SARAM (0-wait)

(4k y 16, Secure Zone, Dual Mapped)

L1 SARAM (0-wait)

(4k y 16, Secure Zone, Dual Mapped)

L0 SARAM (0-wait) (4k y 16,

Secure Zone, Dual Mapped)

L1 SARAM (0-wait) (4k y 16,

Secure Zone, Dual Mapped)

128-bit Password

0x3E 8000

Prog Space

Peripheral Frame 0

Peripheral Frame 1

(protected)

Peripheral Frame 2

(protected)

PIE Vector − RAM

(256 x 16)

(Enabled if ENPIE = 1)

Vectors (32 y 32)

(enabled if VMAP = 1, ENPIE = 0)

0x00 0E00

TMS320F28044

Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

Memory blocks are not to scale.

Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.

User program cannot access these memory maps in program space.

“ Protected” means the order of Write followed by Read operations is preserved rather than the pipeline order.

Certain memory ranges are EALLOW protected against spurious writes after configuration.

Figure 3-2. F28044 Memory Map

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