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GL830 Datasheet(PDF) 20 Page - GENESYS LOGIC |
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GL830 Datasheet(HTML) 20 Page - GENESYS LOGIC |
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20 / 29 page ![]() GL830 USB2.0 to SATA Bridge Controller ©2007 Genesys Logic Inc. - All rights reserved. Page 20 Miscellaneous Interface Pin Name Pin# Type Description TEST 23 I (pd) Test Mode Input X2 92 B Crystal Output X1 93 I Crystal Input HRST_ 9 I (pu) Reset Pin MODE0,1 19,49 I (pd) Mode Select 00=> USB to SATA; 10=> eSATA to SATA; 01=> USB to PATA; 11=> SATA to PATA When MODE0,1=11, PIO1=0 is device mode. When MODE0,1=11, PIO1=1 is host mode. GPIO0~4 1,61,55,2, 64 B (pu) General Purpose I/O #0~#4 PIO0~4 33,34,57, 4,3 B (pd) Programmable I/O #0~#4 TXD 24 O (pu) 8051 UART TXD RXD 25 B (pu) 8051 UART RXD SPDSEL 128 I (pd) 0 => force in 1.5G; 1 => negotiate interface speed with attached device (1.5G or 3G) PHYRDY 63 O SATA PHY ready T_ROM 59 I (pd) 0 => Internal ROM; 1 => External ROM ROM_A0~14 35,31,27, 15,11,5, 125,123, 122,124, 126,7,13, 22,29 O ROM Address #0~#14 ROM_D0~7 37,41,45, 82,84,53, 43,39 B (pd) ROM Data #0~#7 NC 80,97,98, 99,100, 101,102, 103 - No connection Notation: Type O Output I Input B Bi-directional B/I Bi-directional, default input B/O Bi-directional, default output P Power / Ground A Analog |
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