AP64203Q

Document number: DS46205 Rev. 2 - 2

21 of 25

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AP64203Q

Application Information (continued)

Compensation design goals are the following:

1.

Crossover frequency, fC, of approximately 1/10

th of the switching frequency.

2.

Phase margin > 40

.

3.

Gain margin > 10dB in magnitude.

The loop gain at the crossover frequency has a unity gain. Therefore, the value of the top feedback resistance is determined by:

������1 =

127������

������������������������������������������������

Where, CO is the total output capacitance seen by the regulator. This may include ceramic high frequency decoupling and bulk output capacitors.

Ceramic will have derating factor by approximately 40% depending on dielectric, voltage stress, and thermal.

An additional zero contribution due to R1 and C4 can boost the phase margin. Put the compensator zero between 1/2fC to fC frequency.

������4 =

1

2������������������������1