R1121

RISC DSP Communication

16 Bit RISC Micro Processor

Specifications subject to change without notice, contact your sales representatives for the most update information.

RDC Confidential

Page 2 of 5

REV 1.0 May. 03 2007

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Features

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CPU Core

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RDC’s proprietary RISC architecture

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Five-stages pipeline

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Operation frequency: 80MHz,

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Support CPU ID

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Supports 32 PIO pins

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Static Design & Synthesizable design

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External bus, Internal bus and core in the same

clock base

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Bus interface

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Multiplexed address and Data bus

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With 8-bit or 16-bit boot ROM bus size

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Supports direct address bus [A19 : A0]

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8-bit or 16-bit external bus dynamic access

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ROM/RAM/DRAM Controller and Addressing

Space

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1M byte memory address space

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64K byte I/O space

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Support 64kx16, 128kx16, 256kx16 EDO or FP

DRAM with auto-refresh control

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Software

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compatible with generic 80C186 microprocessor

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Asynchronous Serial Channels

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Support two Asynchronous serial channels with

hardware handshaking signals.

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Interrupt Controller

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The interrupt controller with seven maskable

external interrupts and one non-maskable

external interrupt (NMI)

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Two Independent DMA Channels

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Integrate PLL(*1~*8)

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Programmable Chip-select Logic

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Programmable chip-select logic for Memory or

I/O bus cycle decoder

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Programmable wait-state generator

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Counter/Timers

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Three independent 16-bit timers and one

independent programmable watchdog timer

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Operating Voltage Range

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Operation voltage: 3.3V

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Input voltage: 2.5V ~ 5V

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Out voltage: 3.3V

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Package Type

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100 Pin PQFP & LQFP

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A Green Product