R1122

R

R

16-BIT RISC MICROCONTROLLER

Specifications subject to change without notice, contact your sales representatives for the most update information.

Page 2 of 5

REV 1.0 Jun.05 2006

1.

Features

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Five-stage pipeline

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RISC architecture

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Integrated PLL (*1~*8)

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Maximum frequency: 80 MHz; the external bus,

internal bus and core are operating in the same

clock base

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Static & synthesizable design

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Bus interface

- A multiplexed address and data bus which is

compatible with the 80C186 microprocessor

- Supports a direct address bus A[19:0]

- 1M-byte memory address space

- 64K-byte I/O space

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Software is compatible with the 80C186

microprocessor

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Supports two asynchronous serial channels with

hardware handshaking signals

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Supports CPU ID

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Supports 32 PIO pins

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Three independent 16-bit timers and one

independent watchdog timer

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The Interrupt controller with seven maskable

external interrupts and one non-maskable external

interrupt

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Two independent DMA channels

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Programmable chip-select logic for memory or I/O

bus cycle decoder

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Programmable wait-state generators

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The I/O pin output is 3.3 volt level and the input

3.3 to 5 volt tolerance.

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3.3V operation voltage

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Supports serial port/ DMA transfers

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With 8-bit or 16-bit boot ROM bus size

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A green product

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Package Type

- PQFP100 pins & LQFP100 pins