R1122I

R

R

16-BIT RISC MICROCONTROLLER

Specifications subject to change without notice, contact your sales representatives for the most update information.

Page 2 of 5

REV 1.0 Jun.13 2006

1.

Features

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Five-stages pipeline

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RISC architecture

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Static Design & Synthesizable design

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Integrate PLL(*1~*8)

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Maximum frequency is 40MHz, External bus,

Internal bus and core are in the same clock base

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Bus interface

- Multiplexed address and Data bus

- Supports direct address bus [A19: A0]

- 8-bit or 16-bit external bus dynamic access

- 1M byte memory address space

- 64K byte I/O space

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Software is compatible with generic 80C186

microprocessor

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Support two Asynchronous serial channels with

hardware handshaking signals.

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Support CPU ID

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Supports 32 PIO pins

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Support 64kx16, 128kx16, 256kx16 EDO or FP DRAM

with auto-refresh control

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Three independent 16-bit timers and one independent

programmable watchdog timer

external interrupts and one non-maskable external

interrupt(NMI)

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Two independent DMA channels

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The I/O pin output is 3.3 volt level and the input

is 3.3 volt to 5 volt tolerance

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3.3V operation voltage

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Programmable chip-select logic for Memory or

I/O bus cycle decoder

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Programmable wait-state generator

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Boot ROM bus size with 8-bit or 16-bit

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A green product

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Package Type

- PQFP100 pins & LQFP100 pins