R2010

R

R

FAST ETHERNET RISC PROCESSOR

Specifications subject to change without notice, contact your sales representatives for the most update information.

Page 3 of 4

REV 1.0 Nov. 28 2005

2.

Block Diagram

DMA

Unit

Chip

Select

Unit

Refresh

Control

Unit

SDRAM/Bus

Interface

Unit

PIO

Unit

Timer Control

Unit

Interrupt

Control Unit

Clock and

Power

Management

16550 UART

Serial

Port0

Instruction

Queue (64bits)

Instruction

Decoder

Register

File

General,

Segment,

Eflag Register

ALU

(Special,

Logic,

Adder,

BSF)

Micro

ROM

EA / LA

Address

Control Signal

Execution

Unit

X1

X2

CLKOUTA

INT6-INT5

INT0

TMRIN0

TMROUT0

TMRIN1

TMROUT1

DRQ0

DRQ1

SOUT0

SIN0

A[20:0]

D[15:0]

ALE

RD_n

VCC

GND

MCS_n

UCS_n

PCS5_n, PCS3_n,

PCS2_n, PCS0_n

ARDY

WHB_n

16550 UART

Serial

Port1

INT1

INT2

RST_n

MAC

MII

SD_CLK

WE_n

CAS_n

RAS_n

BA[1:0]

DCD0_n

DTR0_n

DSR0_n

RTS0_n

CTS0_n

RI0_n

SOUT1

SIN1

RTS1_n

CTS1_n

WR_n/BWSEL

Cache

WLB_n