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NCP51152 Datasheet(PDF) 21 Page - ON Semiconductor |
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NCP51152 Datasheet(HTML) 21 Page - ON Semiconductor |
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21 / 25 page ![]() NCP51152 www.onsemi.com 21 Figure 51. Recommended Layer Stack 10 mils 0.25 mm 10 mils 0.25 mm 40 mils 1 mm Keep this space free from traces, pads and vias High−speed signal Low−speed signal Ground plane 4 mm 10 mils 0.25 mm 10 mils 0.25 mm 40 mils 1 mm 157 mils Power plane Figure 52 shows the 3D layout of the top view of an evaluation board. The component’s location of the PCB cutout between primary and secondary sides ensures isolation performance. Figure 52. 3−D PCB View Figure 53 shows the top and bottom layer traces and copper of printed circuit board layout. (A) Top & Bottom View (B) Top View (C) Bottom View Figure 53. Printed Circuit Board |
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