TAS5028A datasheet(32/82 Pages) TI

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TAS5028A Controls and Status

SLES112 — June 2004

TAS5028A

TAS5028A Controls and Status

The TAS5028A provides control and status information from both the I2C registers and device pins.

This section describes some of these controls and status functions. The I2C summary and detailed register

descriptions are contained in sections at the end of this document.

2.1

I2C Status Registers

The TAS5028A has two status registers that provide general device information. These are the general status

2.1.1 General Status Register (0x01)

•

Device identification code

•

Clip indicator – The TAS5028A has a clipping indicator. Writing to the register clears the indicator.

•

Bank switching is busy

2.1.2 Error Status Register (0x02)

•

No internal errors (the valid signal is high)

•

A clock error has occurred – These are sticky bits that are cleared by writing to the register.

−

LRCLK error – When the number of MCLKs per LRCLK is incorrect

−

SCLK error – When the number of SCLKS per LRCLK is incorrect

−

Frame slip – When the number of MCLKs per LRCLK changes by more than 10 MCLK cycles

−

PLL phase-lock error

•

This error status register is normally used for system development only.

2.2

TAS5028A Pin Controls

The TAS5028A provide a number of terminal controls to manage the device operation. These controls are:

•

RESET

•

PDN

•

BKND_ERR

•

HP_SEL

•

MUTE

2.2.1 Reset (RESET)

The TAS5028A is placed in the reset mode by setting the RESET terminal low or by the power up reset circuitry

when power is applied.

RESET is an asynchronous control signal that restores the TAS5028A to the hard mute state (M). Master

volume is immediately set to full attenuation (there is no ramp down). Reset initiates the device reset without

an MCLK input. As long as the RESET terminal is held low, the device is in the reset state. During reset, all

I2C and serial data bus operations are ignored.

Table 2−1 shows the device output signals while RESET is active.

Table 2−1. Device Outputs During Reset

SIGNAL

SIGNAL STATE

Valid

Low

PWM P-outputs

Low (M-state)

PWM M-outputs

Low (M-state)

SDA

Signal input (not driven)

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