R8820

RISC DSP Communication

16-Bit RISC Microcontroller

Specifications subject to change without notice, contact your sales representatives for the most update information.

REV 1.0

May. 31 2007

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1. Features

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CPU Core

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RDC’s proprietary RISC architecture

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Five-stage pipeline

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CPU clock speed up to 25 MHz

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Supports CPU ID

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Supports 32 PIO pins

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Static & synthesizable design

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Bus Interface

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A multiplexed address and data bus which is

compatible with the 80C186 microprocessor

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Supports a non-multiplexed address bus A[19:0]

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ROM/RAM Controller and Addressing Space

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1M-byte memory address space

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64K-byte I/O space

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PSRAM Interface

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PSRAM (Pseudo static RAM) interface with

auto-refresh control

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Two Independent DMA Channels

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Supports serial ports with DMA transfers

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Asynchronous Serial Channels

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Supports two asynchronous serial channels with

hardware handshaking signals

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Interrupt Controller

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The interrupt controller with seven maskable

external interrupts and one non-maskable

external interrupt

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Programmable Chip-select Logic

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Programmable chip-select logic for memory or

I/O bus cycle decoder

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Programmable Wait-state Generators

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Counter/Timers

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Three independent 16-bit timers and one

independent watchdog timer

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Software is compatible with the 80C186

microprocessor

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Operating Voltage Range

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Core voltage: 5V ± 5%

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I/O voltage: 5V ± 10%

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Operating Temperature: -40 ~ +85°C

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Package Type

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100-pin PQFP

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100-pin LQFP

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A Green Product