XGS Family

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3

1 clock lane

1, 2, 3 or 4 data lanes

1 clock lane

1, 2, 3 or 4 data lanes

PIXEL ARRAY

(2592 x 2048)

COLUMN STRUCTURE (GR and GB)

COLUMN ADC (GR and GB)

DIGITAL GAIN / DATA PEDESTAL

COLUMN STRUCTURE (R and B)

COLUMN ADC (R and B)

DIGITAL GAIN / DATA PEDESTAL

HiSPi

HiSPi

DIGITAL MUX

DIGITAL MUX

DIGITAL MUX

DIGITAL MUX

HiSPi

HiSPi

MONITOR_[2:0]

SEQUENCER

TRIG_INT

TRIG_RD

RESET_N

BIAS

I2C/SPI DECODER

SPI

PLL

EXTCLK

Figure 1. Functional Block Diagram (XGS 5000)

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