MPC8280 datasheet(1096/1386 Pages) FREESCALE

1096 / 1386 page

ATM AAL1 Circuit Emulation Service

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

32-36

Freescale Semiconductor

32.10 Outgoing CAS Status Register (OCASSR)

Figure 32-25 shows the layout of the outgoing CAS block status register (OCASSR).

This status register contains sticky bits that give the software application an indication that the CP has

modified the associated CAS block. When the ATM receiver operates in core CAS modify mode

RCT[CCASM=1], the CP generates an interrupt and sets the appropriate sticky bit in OCASSR each time

an AAL1 cell is received with new signaling information (one or more signaling nibble has changed).

Note that this flag bit stays set until it is cleared by software. If new signaling is received and the relevant

sticky bit is already set, the CP updates the CAS block without generating another interrupt.

Table 32-9 describes OCASSR fields.

32.11 Buffer Descriptors

The AAL1 CES controller operates as a multi-channel protocol, performing simultaneous segmenting and

reassembling of transmit and receive data, to and from different sets of memory buffers for all channels.

This behavior makes it necessary to have a separate list of BDs for each channel. Each channel is

configured with two BD lists: one for transmit and the other for receive operations. The amount of BDs’

in the table is defined by the user.

The BD table is a circular list, the last BD in the table holds a wrap indication. When the MPC8280 reaches

the last BD, it returns to the head of the list. Each BD in the TxBD table points to a buffer to send. At the

receive side, the user allocates dedicated buffers to each channel (that is, one BD for each buffer). When

the receiver or transmitter completes writing or reading the buffer, it moves to the next buffer in the list

and optionally issues an interrupt.

32.11.1 Transmit Buffer Operation

The user prepares a table of BDs pointing to the buffers to be sent. The address of the first BD is put in the

channel’s TCT[TBD_BASE]. The transmit process starts when the core issues an atm transmit command.

The CP reads the first TxBD in the table and sends its associated buffer. When the current buffer is

finished, the CP increments TBD_OFFSET, which holds the offset from TBD_BASE to the current BD.

It then reads the next BD in the table. If the BD is ready (TxBD[R] = 1), the CP continues sending. If the

Field

—

MCASB7 MCASB6 MCASB5 MCASB4 MCASB3 MCASB2 MCASB1 MCASB0

Figure 32-25. Outgoing CAS Status Register (OCASSR)

Table 32-9. OCASSR Field Descriptions

Bits

Name

Description

0–7

—

Reserved, should be cleared during initialization.

8, 9,

10, 11,

12, 13,

14, 15

MCASB

n Modify CAS Block n.

When the CP updates this outgoing CAS block, it sets the MCASB

n sticky bit and generates an

interrupt to notify the core that the signaling information has changed in block

n. Each channel

selects the CAS block number in its RCT; see Section 32.9.1.1, “AAL1 CES Protocol-Specific RCT.”

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