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RT3612EB Datasheet(PDF) 26 Page - Richtek Technology Corporation

Part # RT3612EB
Description  2-Phase PWM Controller with Dual Integrated Drivers for IMVP9 CPU Core Power Supply
PDF  47 Pages
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Manufacturer  RICHTEK [Richtek Technology Corporation]
Direct Link  http://www.richtek.com
Logo RICHTEK - Richtek Technology Corporation

RT3612EB Datasheet(HTML) 26 Page - Richtek Technology Corporation

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RT3612EB
26
DS3612EB-02 December 2019
www.richtek.com
©
Copyright 2019 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
Loadline Setting (RLL)
An output voltage loadline (Adaptive Voltage Positioning)
are specified in CPU VR for power saving and output
capacitance reduction. The characteristic of loadline is
that the output voltage decreases by an amount proportional
to the increasing loading current, i.e. the slope between
output voltage and loading current (RLL) is shown in Figure
9. Figure 10 shows how the voltage and current loop
parameters of RT3612EB achieve loadline. The detailed
equation is described as below :
,
i
LL
IMON EQ
CSx
EA2
EA1
Current Loop Gain
A
DCR
3
RR
Voltage Loop Gain
R
R
4
R

Ai is current gain. REA2 / REA1 is defined as ERROR AMP
gain. In order to have better transient performance, the
ERROR AMP gain is suggested to be within 2.2 to 3.6
when ICCMAX >= 45A and within 2.2 to 5 when ICCMAX
< 45A. RLL can be programmed by Ai and REA2 / REA1. Ai
can be selected by PIN-SETTING of Ai[1:0] as listed in
Table 8.
Figure 9. Load-Line (Droop)
VCORE
VID
RLL x ICCMAX
Loadline=-RLL
ICCMAX
Loading
Current
Table 8. PIN-SETTING of Ai[1:0]
Ai[1:0]
Current Gain Setting
00
0.125
01
0.25
10
0.375
11
0.5
Figure 8. Total Current Sense Method
Total Current Sense/ICCMAX Setting/Current
Monitoring
To compensate DCR positive temperature coefficient,
conventional current sense method needs an NTC resistor
for per phase current loop. The RT3612EB adopts a
patented total current sense method that requires only
one NTC resistor for thermal compensation. The NTC
resistor is designed within IMON resistor network on IMON
pin. It is suggested to be placed near the inductor of the
first phase. Figure 8 shows the configuration. All phase
current signals are gathered to IMON pin and converted
to a voltage signal VIMON by RIMON,EQ based on VREF06
pin. VREF06 pin provides 0.6V voltage source (as
presented as VVREF06) while normal operation. The
relationship between VIMON and inductor current ILx is :

,
IMON
VREF06
L1 L2
IMON EQ
CSx
DCR
VV
I +I
R
R

VIMON
− VVREF06 is proportional to output current. VIMON −
VVREF06 is used for output current reporting and loadline
loop-control. VIMON
− VVREF06 is averaged by analog low-
pass filter and then transferred to 8-bit ADC. The digitized
reporting value is scaled such that FFh=ICCMAX. RIMON,EQ
should be designed that VIMON
− VVREF06 = 1.6V while
(IL1+IL2) = ICCMAX. Additionally, sets the desired ICCMAX
by ICCMAX[3:0] of PIN-SETTING table. The PIN-SETTING
value determines intel ICCMAX register (21h) value. The
Alert# is asserted while output current exceeds ICCMAX
(VIMON
− VVREF06 > 1.6V). The behavior is masked during
DVID. For loadline loop-control, VIMON
− VVREF06 is scaled
by a percentage of Ai, that can be selected by PIN-
SETTING of Ai[1:0]. The detailed application is described
in the loadline setting section.
VCORE
ISEN1P
ISEN1N
L
DCR
R
C
+
-
RCS1=680ohm
IL1
ISEN2P
ISEN2N
L
DCR
R
C
+
-
IL2
IMON
+
-
0.6V
VREF06
ICS,PER1
ICS,PER2
RNTC
RIMON,EQ
IIMON2
IIMON1
Gm
Gm
RCS2=680ohm
VIMON
VVREF06



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