TSL213

64

× 1 INTEGRATED OPTO SENSOR

SOES009A – D4059, NOVEMBER 1992 – REVISED AUGUST 1993

POST OFFICE BOX 655303

2

Terminal Functions

PIN

DESCRIPTION

NAME

NO.

DESCRIPTION

AO

3

Analog output

CLK

2

Clock. The clock controls charge transfer, pixel output, and reset.

GND

6, 7

Ground (substrate). All voltages are referenced to the substrate.

NC

5

No internal connection

SI

1

Serial input. The serial input defines the end of the integration period and initiates the pixel output sequence.

VDD

4, 8

Supply voltages. These supply power to the analog and digital circuits.

detailed description

sensor elements

The line of sensor elements, called pixels, consists of 64 discrete photosensing areas. Light energy striking a

pixel generates electron-hole pairs in the region under the pixel. The field generated by the bias on the pixel

causes the electrons to collect in the element while the holes are swept into the substrate. The amount of charge

accumulated in each element is directly proportional to the amount of incident light and the integration time.

device operation

Operation of the 64

× 1 array sensor consists of two time periods: an integration period during which charge is

accumulated in the pixels and an output period during which signals are transferred to the output. The integration

period is defined by the interval between serial-input (SI) pulses and includes the output period (see Figure 1).

The required length of the integration period depends upon the amount of incident light and the desired output

signal level.

sense node

On completion of the integration period, the charge contained in each pixel is transferred in turn to the sense

node under the control of the clock (CLK) and SI signals. The signal voltage generated at this node is directly

proportional to the amount of charge and inversely proportional to the capacitance of the sense node.

reset

An internal reset signal is generated by the nonoverlapping clock generator (NOCG) and occurs every clock

cycle. Reset establishes a known voltage on the sense node in preparation for the next charge transfer. This

voltage is used as a reference level for the differential signal amplifier.

shift register

The 64-bit shift register controls the transfer of charge from the pixels to the output stages and provides timing

signals for the NOCG. The SI signal provides the input to the shift register and is shifted under direct control

of the clock.

The output period is initiated by the presence of the SI input pulse coincident with a rising edge of CLK

at each rising edge of the clock. The output period ends on the rising edge of the 65th clock cycle, at which time

the output assumes the high-impedance state. The 65th clock cycle terminates the output of the last pixel and

clears the shift register in preparation for the next SI pulse. To achieve minimum integration time, the SI pulse

may be present on the 66th rising edge of the clock to immediately reinitiate the output phase. When the output

period has been initiated by an SI pulse, the clock must be allowed to complete 65 positive-going transitions

in order to reset the internal logic to a known state.