RT8101APS datasheet(10/15 Pages) RICHTEK

10 / 15 page

RT8101/A

Preliminary

www.richtek.com

DS8101/A-01 March 2007

1) Modulator Frequency Equations

The modulator transfer function is the small-signal transfer

function of VOUT/VCOMP (output voltage over the error

amplifier output. This transfer function is dominated by a

DC gain, a double pole, and a zero as shown in Figure 7.

The DC gain of the modulator is the input voltage (VIN)

divided by the peak to peak oscillator voltage VOSC. The

output LC filter introduces a double pole, 40dB/decade

gain slope above its corner resonant frequency, and a total

phase lag of 180 degrees. The resonant frequency of the

LC filter is expressed as below:

OUT

ESR

OUT

ESR

The ESR zero is contributed by the ESR associated with

the output capacitance. Note that this requires that the

output capacitor should have enough ESR to satisfy

stability requirements. The ESR zero of the output

capacitor is expressed as follows :

2) Compensation Frequency Equations

The compensation network consists of the error amplifier

and the impedance networks ZC and ZF as shown in

Figure 6.

Figure 6. Compensation Loop

fZ1

fP1

REF

COMP

OUT

Feedback Compensation

The RT8101/A is a voltage mode controller. The control

loop is a single voltage feedback path including a

compensator and modulator as shown in Figure 5. The

modulator consists of the PWM comparator and power

stage. The PWM comparator compares error amplifier EA

output (COMP) with oscillator (OSC) sawtooth wave to

provide a pulse-width modulated (PWM) with an amplitude

of VIN at the PHASE node. The PWM wave is smoothed

by the output filter LOUT and COUT. The output voltage (VOUT)

is sensed and fed to the inverting input of the error amplifier.

A well-designed compensator regulates the output voltage

to the reference voltage VREF with fast transient response

and good stability.

In order to achieve fast transient response and accurate

output regulation, an adequate compensator design is

necessary. The goal of the compensation network is to

provide adequate phase margin (greater than 45 degrees)

and the highest 0dB crossing frequency. It is also

recommended to manipulate loop frequency response that

its gain crosses over 0dB at a slope of

−20dB/dec.

Figure 5. Closed Loop

OSC

ΔVOSC

ZFB

ZIN

VIN

Driver

REF

PWM

Comparator

COMP

REF

ZFB

ZIN

VOUT

COMP

ESR

PHASE

COUT

VOUT

LOUT

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