Advanced CMOS Logic – 54AC00

Rev 1.0

19/02/21

Quad 2-Input NAND Gates in bare die form

Description

Features:



Outputs Sink/Source 24mA

54AC00 provides x4 independent 2-input NAND gates

performing the Boolean function Y = A • B or Y = A + B.

The device is fabricated using a 1.5µm 5V CMOS process

combining high speed LSTTL performance with CMOS low

power. Internal circuitry comprises of 3 stages and includes

buffered output for high noise immunity and stability.

Device inputs are compatible with standard CMOS outputs;

with pull-up resistors, they are compatible with LSTTL

outputs. All inputs are equipped with protection circuits

against static discharge and transient excess voltage.



Low Input Current: 1µA



Outputs directly interface CMOS, NMOS and TTL



Operating Voltage Range: 2V to 6V



CMOS High Noise Immunity



Function compatible with 54HC00 or 54LS00



Full Military Temperature Range.

Ordering Information

Die Dimensions in µm (mils)

The following part suffixes apply:



No suffix - MIL-STD-883 /2010B Visual Inspection

1200 (47)



“H” - MIL-STD-883 /2010B Visual Inspection

+ MIL-PRF-38534 Class H LAT



“K” - MIL-STD-883 /2010A Visual Inspection (Space)

+ MIL-PRF-38534 Class K LAT

LAT = Lot Acceptance Test.

For further information on LAT process flows see below.

www.siliconsupplies.com\quality\bare-die-lot-qualification

Supply Formats:

Mechanical Specification



Default – Die in Waffle Pack (400 per tray capacity)

1200 x 1200

µm

Die Size (Unsawn)

47 x 47

mils



Sawn Wafer on Tape – On request

120 x 120

µm

Minimum Bond Pad Size

4.72 x 4.72

mils



Unsawn Wafer – On request

350 (±20)

µm

Die Thickness

13.78 (±0.79)

mils



Die Thickness <> 350µm(14 Mils) – On request



Assembled into Ceramic Package – On request

Top Metal Composition

Al 1%Si 1.1µm

Back Metal Composition

N/A – Bare Si

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