High Speed CMOS Logic – 54HC393

Rev 1.0

7/5/2019

 

 

LIMITS

PARAMETER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SYMBOL

VCC

CONDITIONS

25°C

UNITS

85°C

FULL RANGE

4

2V

290

365

435

4.5V

58

73

87

Maximum Propagation

Delay, Clock to Q3

CL = 50pF,

Input

(Figure 1, 3)

tPLH, tPHL

ns

tr = tf = 6ns

6.0V

49

62

74

2V

165

205

250

4.5V

33

41

50

Maximum Propagation

Delay, Reset to any Q

(Figure 2, 3)

tPHL

6.0V

CL = 50pF,

Input

tr = tf = 6ns

ns

28

35

43

2V

75

95

110

4.5V

15

19

22

Maximum Output

Transition Time,

Any Output

(Figure 1, 3)

tTLH, tTHL

6.0V

CL = 50pF,

Input

tr = tf = 6ns

13

16

19

ns

Maximum Input

Capacitance

CIN

-

-

10

10

10

pF

TYPICAL

Power Dissipation

Capacitance Per Gate

6

TJ = 25°C,

VCC =5.0V

CPD

-

40

pF

AC Electrical Characteristics Continued5

Timing Requirements5

LIMITS

PARAMETER

SYMBOL

VCC

CONDITIONS

25°C

85°C

FULL RANGE

5

UNITS

2.0V

50

65

75

4.5V

10

13

15

Minimum Recovery

Time, Reset Inactive to

Clock

Input

(Figure 2)

trec

ns

tr = tf = 6ns

9

11

6.0V

13

2.0V

80

100

120

4.5V

16

20

24

Minimum Pulse Width,

Clock

(Figure 1)

tw

6.0V

Input

tr = tf = 6ns

14

17

20

ns

2.0V

125

155

190

4.5V

25

31

38

Minimum Pulse Width,

Reset

(Figure 2)

tw

6.0V

Input

tr = tf = 6ns

21

26

32

ns

2.0V

1000

1000

1000

4.5V

500

500

500

Maximum Input Rise

and Fall Times

(Figure 1)

tr, tf

Input

tr = tf = 6ns

6.0V

400

400

400

ns

5. Not production tested in die form, characterized by chip design and tested in package.

6. Used to determine the no-load dynamic power consumption: PD = CPD VCC

2f + ICC VCC.

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