High Speed CMOS Logic – 74HC244 

Rev 1.1

01/05/18

 

AC Electrical Characteristics5

 

LIMITS

PARAMETER

SYMBOL

VCC

CONDITIONS

FULL RANGE

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

25°C

85°C

UNITS

2.0V

96

115

115

3.0V

50

60

60

4.5V

18

23

23

Maximum Propagation

Delay,

CL = 50pF,

A to YA

or B to YB

(Figure 1, 3)

tPLH, tPHL

ns

tr = tf = 6ns

6.0V

15

20

20

2.0V

110

140

140

3.0V

60

70

70

4.5V

22

28

28

Maximum Propagation

Delay,

CL = 50pF,

Output Enable

to YA or YB

(Figure 2,4)

tPLZ, tPHZ

ns

tr = tf = 6ns

6.0V

19

24

24

2.0V

110

140

140

3.0

60

70

70

4.5V

22

28

28

Maximum Propagation

Delay,

CL = 50pF,

Output Enable

to YA or YB

(Figure 2,4)

tPZL, tPZH

ns

tr = tf = 6ns

6.0V

19

24

24

2.0V

60

75

75

3.0V

23

27

27

4.5V

12

15

15

Maximum Output Rise

CL = 50pF,

and Fall Time

(Figure 1, 3)

tTLH, tTHL

ns

tr = tf = 6ns

6.0V

10

13

13

Maximum Input

Capacitance

CIN

-

-

10

10

10

pF

Maximum Three-State

Output Capacitance

(Output in High-

Impedance State)

COUT

-

-

15

15

15

pF

TYPICAL

Power Dissipation

TA = 25°C,

pF

Capacitance

(Per Buffer)

5

CPD

-

VCC = 5.0V

34

5. Not production tested in die form, characterized by chip design and tested in package LAT.

6. Used to determine the no-load dynamic power consumption: PD = CPD VCC

2f + ICC VCC.

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