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LAN9218 Datasheet(PDF) 13 Page - SMSC Corporation |
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LAN9218 Datasheet(HTML) 13 Page - SMSC Corporation |
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13 / 133 page  High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX Datasheet SMSC LAN9218 13 Revision 1.8 (06-06-07) DATASHEET 1.11 Host Bus Interface (SRAM Interface) The host bus interface provides a FIFO interface for the transmit and receive data paths, as well as an interface for the LAN9218 Control and Status Registers (CSR’s). The host bus interface is the primary bus for connection to the embedded host system. This interface models an asynchronous SRAM. TX FIFO, RX FIFO, and CSR’s are accessed through this interface. Programmed I/O transactions are supported. The LAN9218 host bus interface supports 32-bit and 16-bit bus transfers. Internally, all data paths are 32-bits wide. The LAN9218 can be interfaced to either Big-Endian or Little-Endian processors. |
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