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Die Size (Unsawn)

1270 x 1320

50 x 51

µm

mils

Minimum Bond Pad Size

108 x 108

4.25 x 4.25

µm

mils

Die Thickness

350 (±20)

13.78 (±0.79)

µm

mils

Top Metal Composition

Al 1%Si 1.1µm

Back Metal Composition

N/A – Bare Si

High Speed CMOS Logic – 54HC27

Triple 3-Input NOR Gate in bare die form

Output Drive Capability: 10 LSTTL Loads

Low Input Current: 1µA

Outputs directly interface CMOS, NMOS and TTL

Operating Voltage Range: 2V to 6V

Function compatible with 54LS27

High Noise Immunity CMOS process

Full Military Temperature Range.

Rev 1.0

22/04/19

Features:

Ordering Information

The following part suffixes apply:

No suffix - MIL-STD-883 /2010B Visual Inspection

“H” - MIL-STD-883 /2010B Visual Inspection

+ MIL-PRF-38534 Class H LAT

“K” - MIL-STD-883 /2010A Visual Inspection (Space)

+ MIL-PRF-38534 Class K LAT

LAT = Lot Acceptance Test.

For further information on LAT process flows see below.

www.siliconsupplies.com\quality\bare-die-lot-qualification

Supply Formats:

Mechanical Specification

Default – Die in Waffle Pack (400 per tray capacity)

Sawn Wafer on Tape – On request

Unsawn Wafer – On request

Die Thickness <> 350µm(14 Mils) – On request

Assembled into Ceramic Package – On request

The 54HC27 triple 3-Input NOR Gate is fabricated on a

2.5µm 5V CMOS process combining high speed LSTTL

performance with CMOS low power The device contains

three independent 3-input NOR gates performing Boolean

function Y = (A + B + C) or Y = A • B • C in positive logic.

Internal circuitry comprises of three stages and includes

buffered output for high noise immunity and stability. Inputs

are compatible with standard CMOS outputs; with pull-up

resistors, they are compatible with LSTTL outputs.

Description

Die Dimensions in µm (mils)

1270 (50)