PCM1609APT datasheet(14/43 Pages) TI

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AUDIO SERIAL INTERFACE

AUDIO DATA FORMATS AND TIMING

PCM1609A

SLES145A – AUGUST 2005 – REVISED AUGUST 2006

The audio serial interface for the PCM1609A consists of a 5-wire synchronous serial port. It includes LRCK

(pin 41), BCK (pin 40), DATA1 (pin 45), DATA2 (pin 46), DATA3 (pin 47), and DATA4 (pin 31). BCK is the serial

audio bit clock, and is used to clock the serial data present on DATA1, DATA2, DATA3, and DATA4 into the

audio interface serial shift register. Serial data is clocked into the PCM1609A on the rising edge of BCK. LRCK

is the serial audio left/right word clock. It is used to latch serial data into the serial audio interface internal

registers.

Both LRCK and BCK must be synchronous to the system clock. Ideally, it is recommended that LRCK and BCK

be derived from the system clock input, SCKI. LRCK is operated at the sampling frequency (fS). BCK can be

operated at 32, 48, or 64 times the sampling frequency (I2S format does not support BCK = 32 fS).

Internal operation of the PCM1609A is synchronized with LRCK. Accordingly, internal operation of the device is

suspended when the sampling rate clock (LRCK) is changed, or when SCKI and/or BCK is interrupted at least

for a 3-bit clock cycle. If SCKI, BCK, and LRCK are provided continuously after this suspended state, the

internal operation is resynchronized automatically within a period of less than 3/fS. During this resynchronization

period and for a 3/fS time thereafter, the analog outputs are forced to the bipolar zero level, VCC/2. External

resetting is not required.

The PCM1609A supports industry-standard audio data formats, including standard, I2S, and left-justified (see

Figure 22). Data formats are selected using the format bits, FMT[2:0], in register 9. The default data format is

24-bit standard. All formats require binary 2s complement, MSB-first audio data. See Figure 23 for a detailed

timing diagram of the serial audio interface.

DATA1, DATA2, DATA3, and DATA4 each carry two audio channels, designated as the left and right channels.

The left-channel data always precedes the right-channel data in the serial data stream for all data formats.

Table 2 shows the mapping of the digital input data to the analog output pins.

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