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Issue 1.1.0

2021-09-28

TEWS TECHNOLOGIES GmbH

Am Bahnhof 7

25469 Halstenbek, Germany

Phone: +49 (0) 4101 4058 0

Fax: +49 (0) 4101 4058 19

e-mail: info@tews.com

www.tews.com

The Embedded I/O Company

TAMC532 32 x 12/14 Bit 50/75 Msps ADC for MTCA.4 Rear-I/O

Application Information

The TAMC532 is an Advanced Mezzanine Card (AMC)

according to MTCA.4 (MicroTCA Enhancements for Rear

I/O and Precision Timing). 32 analog input channels allow

sampling of analog signals with 75 Msps at 12 Bit

resolution (optional 50 Msps at 14 Bit).

The TAMC532 utilizes Back-IO via Zone 3 to interface the

ADCs with the signal conditioning located on the µRTM.

This modular concept allows adapting the TAMC532 to

nearly any analog input requirement without changing the

AMC itself.

A very powerful on-board clocking structure enables using

the TAMC532 in nearly all kind of clocking scenarios. A

self-clocked application as well as synchronizing multiple

TAMC532 is possible, allowing applications with up to

several hundred simultaneous sampled channels.

Data readout can be done via several interfaces like e.g.

PCI-Express or two SFP-cages in the front panel.

The on-board DRR3 memory can be used for data

buffering in triggered applications that require subsequent

readout. Assuming sufficient data fabric bandwidth, the

DDR3 memory can also be used as double buffer,

allowing infinite data acquisition.

Up to eight backplane triggers are available, each

configurable as input or output.

The TAMC532 is equipped with a powerful Kintex-7 FPGA

for data preprocessing and transfer. By default, the

Kintex-7 FPGA is configured with a firmware that provides

a very functional readout system and full control over the

numerous clocking and trigger options. It can also be

adapted to customer needs if necessary.

In-circuit programming and debugging of the FPGA design

(e.g. using Xilinx “ChipScope”) is supported. The Program

and Debug Box TA900 or the standard Xilinx JTAG

header allows access to the module while it is inserted in a

system. In addition to the module's JTAG Chain, the

TA900 allows access to the UART of the on-board Module

Management Controller (MMC) and to two user pins of the

FPGA. If a UART core is implemented in the FPGA, serial

communication via the TA900 is possible.

The TA900 can be accessed by USB 2.0 and by a 14-pin

JTAG Header (e.g. for connecting a Xilinx Platform Cable).