Electronic Components Datasheet Search
  English  ▼

X  

TAMC651-DOC Datasheet(PDF) 2 Page - TEWS Technologies GmbH

Part # TAMC651-DOC
Description  Spartan-6 FPGA AMC for MTCA.4 Rear-I/O
PDF  3 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TEWS [TEWS Technologies GmbH]
Direct Link  https://www.tews.com/
Logo TEWS - TEWS Technologies GmbH

TAMC651-DOC Datasheet(HTML) 2 Page - TEWS Technologies GmbH

  TAMC651-DOC Datasheet HTML 1Page - TEWS Technologies GmbH TAMC651-DOC Datasheet HTML 2Page - TEWS Technologies GmbH TAMC651-DOC Datasheet HTML 3Page - TEWS Technologies GmbH  
Zoom Inzoom in Zoom Outzoom out
 2 / 3 page
background image
The Embedded I/O Company
Please note: The basic example design requires the
Embedded Development Kit (EDK), which is part of the
Embedded or System Edition of the ISE Design Suite from
Xilinx (downloadable from www.xilinx.com, a 30 day
evaluation license is available).
Software support for the basic design example of the
TAMC651-FDK will be available for all major operating
systems.
The TAMC651 can also be accessed via the TA900
program/debug
box
(USB
2.0
and/or
14-pin
JTAG
Header).
For First-Time-Buyers the TA900, the TAMC651-ED and
TAMC651-FDK are recommended.
Technical Information
 Form Factor: PICMG AMC.0 Module
 Double width
 Mid-Size or Full-Size front panel
 Front panel mechanics and Zone 3 interface
according to MTCA.4
 PCIe x1 link (AMC.1 Type 1 compliant)
 M-LVDS transceivers for AMC ports 12-15 (point-to-
point) and AMC ports 17-20 (multi-point)
 Spartan-6 FPGA
 Xilinx XC6SLX45T-2 or XC6SLX100T-2
 FPGA configuration options
 Xilinx Platform Flash
 SPI serial Flash
 JTAG Header
 DDR3 SDRAM bank, 64M x 16 (128 MB)
 Front Panel LEDs:
 Blue Hot-Swap LED
 Red LED (LED1)
 Green LED (LED2)
 4x user programmable LED
 IPMI V1.5 support
 Programmable Clock Generator
 2 clock lines to FPGA
 1 clock line to SFP/GTP transceiver
 1 clock line to Clock Crosspoint-Switch
 Clock Crosspoint-Switch
 Inputs: Programmable Clock Generator Clock
Output, TCLKA, TCLKB, FPGA Clock output
 Outputs: 2 clock lines to FPGA, 2 clock lines to
Zone 3 interface
 MTCA.4 Zone 3 Interface I/O
 46 differential I/O lines (LVDS), could also be
used as single-ended I/O lines (FPGA bank
supply 2.5V)
 2 differential reference clocks
 2 Spartan-6 GTP transceivers (
μRTM provides
the GTP reference clocks)
 1x SFP Interface at the front plate
 Zone 3 mechanical Key N = 1 (LVDS)
TEWS TECHNOLOGIES GmbH keeps the right to change technical specification without further notice.
All trademarks mentioned are property of their respective owners.
Issue 1.0.2
2017-08-17
TEWS TECHNOLOGIES GmbH
Am Bahnhof 7
25469 Halstenbek, Germany
Phone: +49 (0) 4101 4058 0
Fax: +49 (0) 4101 4058 19
e-mail: info@tews.com
www.tews.com



Html Pages

1 2 3


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com