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09/2009

TEWS TECHNOLOGIES GmbH

Am Bahnhof 7

25469 Halstenbek, Germany

Phone: +49 (0) 4101 4058 0

Fax: +49 (0) 4101 4058 19

e-mail: info@tews.com

www.tews.com

The Embedded I/O Company

TPMC630 Reconfigurable FPGA with 64 TTL I/O / 32 Diff. I/O

Application Information

The TPMC630 is a standard single-width 32 bit PMC

module providing a user configurable FPGA with 300,000

(TPMC630-1x) or 600,000 (TPMC630-2x) system gates.

All local signals from the PCI controller are routed to the

FPGA.

The TPMC630-x0x has 64 ESD-protected TTL lines, the

TPMC630-x1x provides 32 differential I/O lines using

EIA-422 / EIA-485

compatible,

ESD-protected

line

transceivers. The TPMC630-x2x provides 32 TTL and 16

differential I/Os. All lines are individually programmable as

input or output. The receivers are always enabled, which

allows determining the state of each I/O line at any time.

This can be used as read back function for lines

configured as outputs. Each TTL I/O line has a pull-up

resistor. The pull-up voltage is selectable to be either

+3.3V or +5V. The differential I/O lines are terminated by

120Ω resistors.

The FPGA is configured by a serial Flash. The Flash

device is in-system programmable via driver software over

the PCI bus. An in-circuit debugging option is available via

an optionally mountable JTAG header (on the backside of

the board) for readback and real-time debugging of the

FPGA design (using Xilinx “ChipScope”).

A programmable clock generator supplies up to six

different

clock

frequencies

between

200 kHz

and

166 MHz. All outputs are available at the FPGA, one clock

source is in addition used as the local clock signal for the

PCI controller. The clock generator settings are stored in

an EEPROM and can be changed by the driver software

through PCI9030 GPIO pins.

The configuration EEPROM of the PCI controller can also

be modified by the driver software, to adapt address

spaces etc.

User applications can be developed using the design

software ISE WebPACK which can be downloaded free of

charge from www.xilinx.com.

The TPMC630 provides front panel I/O via a HD68 SCSI-3

type connector and rear panel I/O via P14.

For First Time Users the Engineering Documentation

TPMC630-ED

is

recommended.

The

Engineering

Documentation includes TPMC630-DOC, schematics,

data sheets / application notes of the components and well

documented sample VHDL source code.

Software

Support

(TPMC630-SW-xx)

for

different

operating systems is available.

Technical Information

Standard single-width 32 bit PMC module conforming

to IEEE P1386.1

PCI 2.1 compliant interface

3.3V and 5V PCI Signaling Voltage

Board size: 149 mm x 74 mm

TPMC630-1x: Xilinx XC2S300E-6 Spartan-IIE FPGA

configured by serial Flash XCF02S

TPMC630-2x: Xilinx XC2S600E-6 Spartan-IIE FPGA

configured by serial Flash XCF04S

Flash device in-system programmable

32 bit PCI target interface by PLX PCI9030

FPGA clock options:

Local clock oscillator

PLL programmable clock generator (200 KHz –

166 MHz), 6 clock outputs connected to FPGA

I/O lines

64 TTL I/O (-10), 32 differential I/O (-11) or

32 TTL I/O and 16 differential I/O (-12)

TTL signaling voltage (maximum current:

+/-32mA) or EIA-422/-485 signaling level

direction individually programmable

I/O access:

64 I/O lines on HD68 front connector, parallel to

up to 64 I/O lines on rear connector P14

Operating temperature: -40°C to +85°C

64 x TTL I/O

Drivers

(TPMC630-10)

or 32 x

Differential

Drivers

(TPMC630-11)

or

32 x TTL I/O

and 16 x

Differential

Drivers

(TPMC630-12)

Programmable

Clocks

Serial

Flash

XILINX FPGA

SPARTAN IIE

XC2S300 E

(TPMC630-1x)

or XC2S600E

(TPMC630-2x)

PCI

Controller

JTAG Header