1.

General description

The PCA9306 allows bidirectional voltage translations between 1.2 V and 5 V without the

to be made with minimal propagation delay. When EN is HIGH, the translator switch is on,

and the SCL1 and SDA1 I/O are connected to the SCL2 and SDA2 I/O, respectively,

allowing bidirectional data flow between ports. When EN is LOW, the translator switch is

off, and a high-impedance state exists between ports.

and bus length. Using the PCA9306 enables the system designer to isolate two halves of

the enable pin. The PCA9306 is not a bus buffer like the PCA9509 or PCA9517 that

provides level translation and physically isolates the capacitance to either side of the bus

even when both sides are connected.

The PCA9306 can also be used to run two buses, one at 400 kHz operating frequency

and the other at 100 kHz operating frequency. If the two buses are operating at different

frequencies, the 100 kHz bus must be isolated when the 400 kHz operation of the other

bus is required. If the master is running at 400 kHz, the maximum system operating

frequency may be less than 400 kHz because of the delays added by the translator.

HIGH levels on the translator’s bus. The PCA9306 has a standard open-collector

but each side of the translator must have a pull-up resistor. The device is designed to work

SMBus devices.

When the SDA1 or SDA2 port is LOW, the clamp is in the ON-state and a low resistance

connection exists between the SDA1 and SDA2 ports. Assuming the higher voltage is on

the SDA2 port when the SDA2 port is HIGH, the voltage on the SDA1 port is limited to the

voltage set by VREF1. When the SDA1 port is HIGH, the SDA2 port is pulled to the drain

translation between higher and lower voltages selected by the user without the need for

directional control. The SCL1/SCL2 channel also functions as the SDA1/SDA2 channel.

PCA9306

Rev. 02 — 21 February 2007

Product data sheet