74ACT11112

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOP

WITH CLEAR AND PRESET

SCAS064A – D3339, JUNE 1989 – REVISED APRIL 1993

POST OFFICE BOX 655303

Copyright

2–1

From External Disturbance

PCB Layout

Minimize High-Speed Switching Noise

CMOS) 1-

mm Process

Small-Outline Packages and Standard

Plastic 300-mil DIPs

description

This device contains two independent J-K negative-edge-triggered flip-flops. A low level at the PRE or CLR

input sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive

(high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the

negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to

the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed

without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying

J and K high.

The 74ACT11112 is characterized for operation from – 40

°C to 85°C.

FUNCTION TABLE

INPUTS

OUTPUTS

PRE

CLR

CLK

J

K

Q

Q

L

H

X

X

X

H

L

H

LX

X

X

L

H

L

LX

X

X

H{

H{

H

H

↓

LL

Q0

Q0

H

H

↓

HLH

L

H

H

↓

LHL

H

H

H

↓

H

H

TOGGLE

H

H

H

X

X

Q0

Q0

† This configuration is nonstable; that is, it will not

persist when either PRE or CLR returns to the

inactive (high) level.

D OR N PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

1PRE

1Q

1Q

GND

2Q

2Q

2PRE

2J

1J

1K

1CLK

1CLR

2CLR

2CLK

2K

EPIC is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.