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74AHCT08 Datasheet(PDF) 8 Page - NXP Semiconductors |
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74AHCT08 Datasheet(HTML) 8 Page - NXP Semiconductors |
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8 / 14 page  74AHC_AHCT08_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 14 November 2007 8 of 14 NXP Semiconductors 74AHC08; 74AHCT08 Quad 2-input AND gate Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch. Fig 7. Load circuit for switching times VM VM tW tW 10 % 90 % 0 V VI VI negative pulse positive pulse 0 V VM VM 90 % 10 % tf tr tr tf 001aad983 DUT VCC VCC VI VO RT RL S1 CL open PULSE GENERATOR Table 9. Test data Type Input Load S1 position VI tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ 74AHC08 VCC ≤ 3.0 ns 15 pF, 50 pF 1 k Ω open GND VCC 74AHCT08 3.0 V ≤ 3.0 ns 15 pF, 50 pF 1 k Ω open GND VCC |
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