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DS1822Z/T Datasheet(PDF) 16 Page - Maxim Integrated Products |
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DS1822Z/T Datasheet(HTML) 16 Page - Maxim Integrated Products |
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16 / 21 page ![]() DS1822 16 of 21 The DS1822 samples the 1-Wire bus during a window that lasts from 15 μs to 60μs after the master initiates the write time slot. If the bus is high during the sampling window, a 1 is written to the DS1822. If the line is low, a 0 is written to the DS1822. READ/WRITE TIME SLOT TIMING DIAGRAM Figure 14 READ TIME SLOTS The DS1822 can only transmit data to the master when the master issues read time slots. Therefore, the master must generate read time slots immediately after issuing a Read Scratchpad [BEh] or Read Power Supply [B4h] command, so that the DS1822 can provide the requested data. In addition, the master can generate read time slots after issuing Convert T [44h] or Recall E 2 [B8h] commands to find out the status of the operation as explained in the DS1822 FUNCTION COMMAND section. All read time slots must be a minimum of 60 μs in duration with a minimum of a 1μs recovery time between slots. A read time slot is initiated by the master device pulling the 1-Wire bus low for a minimum of 1 μs and then releasing the bus (see Figure 14). After the master initiates the read time slot, the DS1822 will begin transmitting a 1 or 0 on bus. The DS1822 transmits a 1 by leaving the bus high and transmits a 0 by pulling the bus low. When transmitting a 0, the DS1822 will release the bus by the end of the time slot, and the bus will be pulled back to its high idle state by the pullup resister. Output 45 μs 15 μs VPU GND 1-WIRE BUS 60 μs < T X “0” < 120μs 1 μs < T REC < ∞ DS1822 Samples MIN TYP MAX 15 μs 30 μs > 1 μs MASTER WRITE “0” SLOT MASTER WRITE “1” SLOT VPU GND 1-WIRE BUS 15 μs MASTER READ “0” SLOT MASTER READ “1” SLOT Master samples Master samples START OF SLOT START OF SLOT > 1 μs 1 μs < T REC < ∞ 15 μs 15 μs 30 μs 15 μs DS1822 Samples MIN TYP MAX LINE TYPE LEGEND Bus master pulling low DS1822 pulling low Resistor pullup > 1 μs |
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