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74LVC1G10GM Datasheet(PDF) 3 Page - NXP Semiconductors |
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74LVC1G10GM Datasheet(HTML) 3 Page - NXP Semiconductors |
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3 / 14 page ![]() 74LVC1G10_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 2 October 2007 3 of 14 NXP Semiconductors 74LVC1G10 Single 3-input NAND gate 6. Pinning information 6.1 Pinning 6.2 Pin description 7. Functional description [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. Fig 4. Pin configuration SOT363 and SOT457 Fig 5. Pin configuration SOT886 Fig 6. Pin configuration SOT891 74LVC1G10 AC GND BY 001aag689 1 2 3 6 VCC 5 4 74LVC1G10 GND 001aag690 A B VCC C Y Transparent top view 2 3 1 5 4 6 74LVC1G10 GND 001aag691 A B VCC C Y Transparent top view 2 3 1 5 4 6 Table 3. Pin description Symbol Pin Description A 1 data input GND 2 ground (0 V) B 3 data input Y 4 data output VCC 5 supply voltage C 6 data input Table 4. Function table[1] Input Output A B C Y HHHL L XXH XL XH XXL H |
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