AME, Inc.

5

ATTM01/ATTM02

Processor Thermal Monitor

Rev. B.01

Parameter

Symbol

Test Conditions

Min

Typ

Max Units

Serial Clock Frequency

(Note 3)

100

kHz

START Condition Setup Time

4.7

µs

Repeat START Condition Setup Time

90% to 90%

50

ns

START Condition Hold Time

10% of SMBDATA to 90% of SMBCLK

4

µs

STOP Condition Setup Time

90% of SMBCLK to 90% of SMBDATA

4

µs

Clock Low Period

10% to 10%

4.7

µs

Clock High Period

90% to 90%

4

µs

Data Setup Time

(Note 4)

250

µs

Receive SMBCLK/SMBDATA Rise Time

1

µs

Receive SMBCLK/SMBDATA Fall Time

300

ns

Pulse Width of Spike Suppressed

0

60

ns

SMBus Timeout

25

37

45

ms

SMBus-COMPATIBLE TIMING (Note 2)

µs

Bus Free Time Between STOP and

START Condition

4.7

6. Electrical Specifications

Note 1: All parameters tested at a single temperature. Specifications over temperature are guaranteed by design.

Note 2: Timing specifications guaranteed by design.

Note 3: The serial interface resets when SMBCLK is low for more than t

Note 4: A transition must internally provide at least a hold time to bridge the undefined region (300ns max) of

SMBCLK

’s falling edge.