Analog Integrated Circuit Device Data

8

Freescale Semiconductor

33811

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics

Characteristics noted under conditions 10.5V

Characteristic

Symbol

Min

Typ

Max

Unit

SPI DIGITAL INTERFACE TIMING(10)

Required High State Duration on RESET for Reset to occur(11)

1.0

–

–

µs

Falling Edge of CS to Rising Edge of SCLK

Required Setup Time

100

–

–

ns

Falling Edge of SCLK to Rising Edge of CS

Required Setup Time

0

50

ns

SI to Rising Edge of SCLK

Required Setup Time

16

–

–

ns

Rising Edge of SCLK to SI

Required Hold Time

20

–

–

ns

SI, CS, SCLK Signal Rise Time(12)

–

5.0

–

ns

SI, CS, SCLK Signal Fall Time(12)

–

5.0

–

ns

Time from Falling Edge of CS to SO Low-impedance(13)

–

65

80

ns

Time from Rising Edge of CS to SO High-impedance(14)

–

–

55

ns

Time from Falling Edge of SCLK to SO Data Valid(15)

–

65

90

ns

Sequential Transfer Rate

Time required between data transfers

1.0

µs

Input Capacitance (SI, SCLK)

7

15

pF

Load Capacitance (SO)

200

pF

Tri-state Output Capacitance (SO)

20

pF

WAVEFORM DETECTION TIMINGS

Start of Activation Filter Time(16)

200

400

600

µs

Detection Window Time

40

53

66

ms

Sample Time

72

µs

Notes:

10.

These parameters are guaranteed by design. Production test equipment uses 3.2MHz, 5.0V SPI interface.

11.

This parameter is guaranteed by design, however it is not production tested.

12.

Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.

13.

Time required for valid output status data to be available on SO pin.

14.

Time required for output states data to be terminated at SO pin.

15.

Time required to obtain valid data out from SO following the fall of SCLK with 200pF load.

16.

9 µs guard band included in maximum limit