TMP94C241C datasheet(21/236 Pages) TOSHIBA

21 / 236 page

TMP94C241C

2005-05-10

94C241C-19

3.3.2

Micro DMA

TMP94C241C supports the micro DMA function. For interrupt requests set for micro

DMA, micro DMA processing is performed at the highest priority for maskable interrupts,

regardless of the set interrupt level.

Since the micro DMA has eight channels, it can transfer continuously by the burst

specification which is described later.

(1) Micro DMA operation

When an interrupt request occurs for an interrupt specified by the micro DMA start

vector register, micro DMA sends data to the CPU with the highest priority for

maskable interrupts, regardless of the interrupt level set for the interrupt. If IFF

= 7,

micro DMA request is not accept.

The micro DMA function has eight channels. This allows micro DMA to be set for up

to eight interrupts at the same time.

When micro DMA is accepted, the interrupt request F/F for the micro DMA channel

is cleared, data are transferred (1 byte, 2 bytes, and 4 bytes) once from the transfer

source address to the transfer destination address (the addresses are set in the control

CPU informs a micro DMA transfer end to the interrupt controller. The interrupt

controller generates a micro DMA transfer end interrupt (INTTCn). The CPU clears

the micro DMA start vector register (DMAnV) 0, disables the next micro DMA startup,

and terminates the micro DMA processing. If the decremented result is other than 0,

micro DMA processing is terminated without the burst specification which is described

later. In this case, the transfer end interrupt (INTTCN) is not generated.

When the interrupt source is used only to start micro DMA, the interrupt level must

be set to “0”.

When the interrupt request generates until the interrupt sources are set to the micro

DMA start vector, the CPU performs the general-purpose interrupt processing at the

interrupt level of 1 to 6.

When simultaneously using the same interrupt resource for both the micro DMA and

general-purpose interrupts as described above, set the level of the interrupt source

used to start micro DMA lower than the levels of all other interrupt sources.

Like other maskable interrupts, the priority of the micro DMA transfer end interrupt

is determined by the interrupt level and default priority.

If multiple-channel micro DMA requests occur at the same time, the priority is

determined by the channel numbers, not the interrupt levels. The lower the channel

number, the higher the priority. (CH0 (High) to CH2 (Low).)

The transfer source and transfer destination addresses are set in 32-bit control

registers. However, as only 24-bit addresses are output, the address space available to

micro DMA is 16 Mbytes.

TMP94C241C Datasheet(PDF) 21 Page - Toshiba Semiconductor

TMP94C241C Datasheet(HTML) 21 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL