ST72682 datasheet(15/36 Pages) STMICROELECTRONICS

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ST72682

NAND Flash memory interface

15/36

4.3

Wear levelling

During normal application life, the NAND memory is written and erased (at block level) many

times. The NAND device is guaranteed for a limited number of write operations (about 100

000 cycles). As a consequence, the controller must keep write/erase operations to a

minimum for any individual block.

A method to limit these cycles is to use a “Wear Levelling” scheme between all NAND

memory blocks.

LUT usage

The LUT is used for transfers between a logical address range and a block. It contains free

blocks which are used in the “wear levelling” scheme.

During write command treatment, the firmware calculates the zones, blocks and pages for

data write access. In a block write operation, the firmware applies the following scheme to

avoid block wearing:

●

The least recently-used block is chosen from the free block part of the LUT.

●

Valid data from the old block is copied to the new block.

●

New data from the write command is written to the new block.

●

The old block is erased.

●

The LUT is updated after identifying the new block in the used block part and the old

block in the free block part.

Using this scheme, a logical address range doesn’t correspond to a constant block. A write

command repeated several times to the same logical address writes physically into different

blocks.

This method shares the wearing evenly across all blocks of the concerned zone.

4.4

NAND Flash interface configuration

Applications based on ST72682 can be configured through a dedicated PC software tool.

The NAND memory RE and WE signals frequencies can be independently configured to

30 MHz, 20 MHz, 15 MHz, 12 MHz and 10 MHz.

The logical size reduction factor can be configured to 90% or 50% in the event of having too

many bad blocks. this option resizes the used blocks part of the LUT to 900 or 500.

ST72682 Datasheet(PDF) 15 Page - STMicroelectronics