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are trademarks of their respective owners.

Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

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SYMBOL

docdbusctrl

rst

cs

qmt(31:0)

rd

wr

addr(4:0)

clk

qmr(31:0)

rxd

dmt(31:0)

waddrmt(1:0)

raddrmt(1:0)

enrmt

enwmt

int

dmr(31:0)

waddrmr(3:0)

raddrmr(3:0)

enrmr

enwmr

txd

sclk

1 – data bus can be configured as 8-, 16- or 32- bit depends

on processor’s bus size

2 – byte enable (be) size is set accordingly to data bus size

PINS DESCRIPTI O N

PIN

TYPE

DESCRIPTION

clk

input

Global clock

rst

input

Global reset

cs

input

Chip select

rd

input

Read data strobe

wr

input

Write data strobe

addr(4:0)

input

Host address bus

be(3:0)

2

input

Host byte enable

datai(31:0)

1

input

Host output data bus

qmr(31:0)

input

RX DPRAM data output

qmt(31:0)

input

TX DPRAM data output

rxd

input

CAN receive data

docdbusctrl

input

DoCD debugger input

datao(31:0)

1

output

Host input data bus

int

output

Interrupt signal

dmr(31:0)

output

RX DPRAM data input

waddrmr(3:0)

output

RX DPRAM write address

raddrmr(3:0)

output

RX DPRAM read address

enrmr

output

RX DPRAM read enable

enwmr

output

RX DPRAM write enable

dmt(31:0)

output

TX DPRAM data input

waddrmt(1:0)

output

TX DPRAM write address

raddrmt(1:0)

output

TX DPRAM read address

enrmt

output

TX DPRAM read enable

enwmt

output

TX DPRAM write enable

txd

output

CAN transmit data

sclk

output

SCLK clock output

BLOCK DIAGRAM

Figure below shows the DCAN IP Core block

diagram.

Receive

FIFO

BTL

Bit Timing

Logic

clk

rst

cs

rd

wr

be(3:0)

addr(4:0)

datai(31:0)

IML

Interface

Management

Logic

int

datao(31:0)

TX RAM

interface

TX RAM pins

RX RAM

interface

RX RAM pins

BRP

Baud Rate

Prescaler

EML

Error

Management

Logic

BSP

Bit Stream

Processor

txd

rxd

ACF

Acceptance Filtering

sclk

Interface Management Logic (IML)

– inter-

prets commands from the CPU, provides in-

terrupt and status indication.

Bit Stream Processor (BSP)

– translates

messages into frames and vice versa.

Baud Rate Prescaler (BRP)

– defines the

length of time quantum.

Bit Timing Logic (BTL)

– processes the bit

time, calculates position of the sample point

and performs synchronization.

Error Management Logic (EML)

– is re-

sponsible for fault confinement handling.

Acceptance Filter (ACF)

– decides whether

incoming messages are accepted or not

based upon filter registers settings.

TX/RX RAM interfaces

– interfaces to exter-

nal dual port memories used by the DCAN

core to store received and transmitted

frames.