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DP8051

STRATIX-II

150 MHz 26220 (14.924)

Core performance in terms of Dhrystones

268

1550

26220

0

3000

6000

9000

12000

15000

18000

21000

24000

27000

80C51 (12MHz)

80C310 (33MHz)

DP8051 (150MHz)

Area utilized by the each unit of DP8051 core

in vendor specific technologies is summarized

in table below.

Area

Component

[LC]

[FFs]

CPU*

1620

285

Interrupt Controller

150

40

Power Management Unit

10

5

I/O ports

100

35

Timers

160

50

UART0

210

60

Total area

2250

475

*CPU – consisted of ALU, Opcode Decoder, Control Unit, Program &

Internal & External Memory Interfaces, User SFRs Interface

Core components area utilization in all technologies except

STRATIX-II

Area

Component

[LC]

[FFs]

CPU*

1265

285

Interrupt Controller

115

40

Power Management Unit

10

5

I/O ports

75

35

Timers

125

50

UART0

160

60

Total area

1750

475

*CPU – consisted of ALU, Opcode Decoder, Control Unit, Program &

Internal & External Memory Interfaces, User SFRs Interface

Core components area utilization in STRATIX-II